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ds077 july 28, 2004 www.xilinx.com product specification 1-800-255-7778 ? 2004 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. this document includes all four modules of the spartan?-iie fpga data sheet. module 1: introduction and ordering information ds077-1 (v2.2) july 28, 2004 6pages introduction features general overview product availability user i/o chart ordering information module 2: functional description ds077-2 (v2.1) july 9, 2003 20 pages ? architectural description - spartan-iie array - input/output block - configurable logic block -block ram - clock distribution: delay-locked loop - boundary scan ? development system configuration module 3: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 22 pages dc specifications - absolute maximum ratings - recommended operating conditions - dc characteristics - power-on requirements - dc input and output levels switching characteristics - pin-to-pin parameters - iob switching characteristics - clock distribution characteristics - dll timing parameters - clb switching characteristics - block ram switching characteristics - tbuf switching characteristics - jtag switching characteristics - configuration switching characteristics module 4: pinout tables ds077-4 (2.1) february 14, 2003 54 pages pin definitions pinout tables important note: the spartan-iie 1.8v fpga data sheet is created and published in separate modules. this complete version is provided for easy downloading and searching of the complete document. page, figure, and table numbers begin at 1 for each module, and each module has its own revision history at the end. use the pdf "bookmarks" for easy navigation in this volume. 0 spartan-iie 1.8v fpga family: complete data sheet ds077 july 28, 2004 0 0 product specification r
ds077-1 (v2.2) july 28, 2004 www.xilinx.com 1 product specification 1-800-255-7778 ? 2004 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. introduction the spartan?-iie 1.8v field-programmable gate array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. the seven-member family offers densities ranging from 50,000 to 600,000 system gates, as shown in ta b l e 1 . system performance is supported beyond 200 mhz. spartan-iie devices deliver more gates, i/os, and features per dollar than other fpgas by combining advanced pro- cess technology with a streamlined architecture based on the proven virtex?-e platform. features include block ram (to 288k bits), distributed ram (to 221,184 bits), 19 select- able i/o standards, and four dlls (delay-locked loops). fast, predictable interconnect means that successive design iterations continue to meet timing requirements. the spartan-iie family is a superior alternative to mask-programmed asics. the fpga avoids the initial cost, lengthy development cycles, and inherent risk of conventional asics. also, fpga programmability permits design upgrades in the field with no hardware replacement necessary (impossible with asics). features second generation asic replacement technology - densities as high as 15,552 logic cells with up to 600,000 system gates - streamlined features based on virtex-e architecture - unlimited in-system reprogrammability - very low cost - advanced 0.15 micron technology system level features - selectram+? hierarchical memory: 16 bits/lut distributed ram configurable 4k-bit true dual-port block ram fast interfaces to external ram - fully 3.3v pci compliant to 64 bits at 66 mhz and cardbus compliant - low-power segmented routing architecture - dedicated carry logic for high-speed arithmetic - efficient multiplier support - cascade chain for wide-input functions - abundant registers/latches with enable, set, reset - four dedicated dlls for advanced clock control eliminate clock distribution delay multiply, divide, or phase shift - four primary low-skew global clock distribution nets - ieee 1149.1 compatible boundary scan logic versatile i/o and packaging - pb-free package options - low-cost packages available in all densities - family footprint compatibility in common packages - 19 high-performance interface standards lvttl, lvcmos, hstl, sstl, agp, ctt, gtl lvds and lvpecl differential i/o - up to 205 differential i/o pairs that can be input, output, or bidirectional - hot swap i/o (compactpci friendly) fully supported by powerful xilinx ise development system - fully automatic mapping, placement, and routing - integrated with design entry and verification tools - extensive ip library including dsp functions and soft processors 06 spartan-iie 1.8v fpga family: introduction and ordering information ds077-1 (v2.2) july 28, 2004 0 0 product specification r table 1: spartan-iie fpga family members device logic cells typical system gate range (logic and ram) clb array (r x c) total clbs maximum available user i/o (1) maximum differential i/o pairs distributed ram bits block ram bits xc2s50e 1,728 23,000 - 50,000 16 x 24 384 182 83 24,576 32k xc2s100e 2,700 37,000 - 100,000 20 x 30 600 202 86 38,400 40k xc2s150e 3,888 52,000 - 150,000 24 x 36 864 265 114 55,296 48k XC2S200E 5,292 71,000 - 200,000 28 x 42 1,176 289 120 75,264 56k xc2s300e 6,912 93,000 - 300,000 32 x 48 1,536 329 120 98,304 64k xc2s400e 10,800 145,000 - 400,000 40 x 60 2,400 410 172 153,600 160k xc2s600e 15,552 210,000 - 600,000 48 x 72 3,456 514 205 221,184 288k notes: 1. user i/o counts include the four global clock/user input pins. see details in table 2, page 3
spartan-iie 1.8v fpga family: introduction and ordering information 2 www.xilinx.com ds077-1 (v2.2) july 28, 2004 1-800-255-7778 product specification r general overview the spartan-iie family of fpgas have a regular, flexible, programmable architecture of configurable logic blocks (clbs), surrounded by a perimeter of programmable input/output blocks (iobs). there are four delay-locked loops (dlls), one at each corner of the die. two columns of block ram lie on opposite sides of the die, between the clbs and the iob columns. the xc2s400e has four col- umns and the xc2s600e has six columns of block ram. these functional elements are interconnected by a powerful hierarchy of versatile routing channels (see figure 1 ). spartan-iie fpgas are customized by loading configura- tion data into internal static memory cells. unlimited repro- gramming cycles are possible with this approach. stored values in these cells determine logic functions and intercon- nections implemented in the fpga. configuration data can be read from an external serial prom (master serial mode), or written into the fpga in slave serial, slave parallel, or boundary scan modes. xilinx offers multiple types of low-cost configuration solutions including the platform flash in-system programmable configuration proms. spartan-iie fpgas are typically used in high-volume appli- cations where the versatility of a fast programmable solution adds benefits. spartan-iie fpgas are ideal for shortening product development cycles while offering a cost-effective solution for high volume production. spartan-iie fpgas achieve high-performance, low-cost operation through advanced architecture and semiconduc- tor technology. spartan-iie devices provide system clock rates beyond 200 mhz. in addition to the conventional ben- efits of high-volume programmable logic solutions, spar- tan-iie fpgas also offer on-chip synchronous single-port and dual-port ram (block and distributed form), dll clock drivers, programmable set and reset on all flip-flops, fast carry logic, and many other features. spartan-iie family compared to spartan-ii family higher density and more i/o higher performance unique pinouts in cost-effective packages differential signaling - lv d s, b u s lv d s, lv p e c l v ccint = 1.8v - lower power - 5v tolerance with external resistor - 3v tolerance directly pci, lvttl, and lvcmos2 input buffers powered by v cco instead of v ccint unique larger bitstream figure 1: basic spartan-iie family fpga block diagram dll dll dll dll block ram block ram block ram block ram i/o logic clbs clbs clbs clbs ds077_01_052102
spartan-iie 1.8v fpga family: introduction and ordering information ds077-1 (v2.2) july 28, 2004 www.xilinx.com 3 product specification 1-800-255-7778 r spartan-iie product availability ta b l e 2 shows the maximum user i/os available on the device and the number of user i/os available for each device/package combination. table 2: spartan-iie user i/o chart device maximum user i/o available user i/o according to package type tq144 tqg144 pq208 pqg208 ft256 ftg256 fg456 fgg456 fg676 fgg676 xc2s50e 182 102 146 182 - - xc2s100e 202 102 146 182 202 - xc2s150e 265 - 146 182 265 - XC2S200E 289 - 146 182 289 - xc2s300e 329 - 146 182 329 - xc2s400e 410 - - 182 329 410 xc2s600e 514 - - - 329 514 notes: 1. user i/o counts include the four global clock/user input pins.
spartan-iie 1.8v fpga family: introduction and ordering information 4 www.xilinx.com ds077-1 (v2.2) july 28, 2004 1-800-255-7778 product specification r ordering information spartan-iie devices are available in both standard and pb-free packaging options for all device/package combinations. the pb-free packages include a special "g" character in the ordering code. standard packaging pb-free packaging device part marking xc2s50e -6 pq 208 c device type speed grade temperature range package type number of pins example: ds077-1_03a_072004 xc2s50e -6 pq 208 c device type speed grade temperature range package type number of pins pb-free g example: ds077-1_03b_072004 device ordering options device speed grade package type / number of pins temperature range (t j ) (2) xc2s50e -6 standard performance tq(g)144 144-pin plastic thin qfp c = commercial 0c to +85c xc2s100e -7 higher performance (1) pq(g)208 208-pin plastic qfp i = industrial ?40c to +100c xc2s150e ft(g)256 256-ball fine pitch bga XC2S200E fg(g)456 456-ball fine pitch bga xc2s300e fg(g)676 676-ball fine pitch bga xc2s400e xc2s600e notes: 1. the -7 speed grade is exclusively available in the commercial temperature range. 2. see www.xilinx.com for information on automotive temperature range devices. lot code (numeric) date code sample package with part marking for xc2s50e-6pq208c. xc2s50e pq208xxx0425 xxxxxxxxx 6c spartan device type package speed operating range r r ds077-1_02_072804
spartan-iie 1.8v fpga family: introduction and ordering information ds077-1 (v2.2) july 28, 2004 www.xilinx.com 5 product specification 1-800-255-7778 r the spartan-iie family data sheet ds077-1 , spartan-iie 1.8v fpga family: introduction and ordering information (module 1) ds077-2 , spartan-iie 1.8v fpga family: functional description (module 2) ds077-3 , spartan-iie 1.8v fpga family: dc and switching characteristics (module 3) ds077-4 , spartan-iie 1.8v fpga family: pinout tables (module 4) revision history date version no. description 06/27/02 1.1 updated -7 availability. 11/18/02 2.0 added xc2s400e and xc2s600e. corrected xc2s150e max i/o count and xc2s50e differential i/o count and updated availability. 07/09/03 2.1 noted hot-swap capability. updated ta b l e 2 to show that all products are available. clarified device part marking. 07/28/04 2.2 added information on pb-free packaging options.
spartan-iie 1.8v fpga family: introduction and ordering information 6 www.xilinx.com ds077-1 (v2.2) july 28, 2004 1-800-255-7778 product specification r
ds077-2 (v2.1) july 9, 2003 www.xilinx.com 1 product specification 1-800-255-7778 ? 2003 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. architectural description spartan-iie array the spartan-iie user-programmable gate array, shown in figure 1 , is composed of five major configurable elements: iobs provide the interface between the package pins and the internal logic clbs provide the functional elements for constructing most logic dedicated block ram memories of 4096 bits each clock dlls for clock-distribution delay compensation and clock domain control versatile multi-level interconnect structure as can be seen in figure 1 , the clbs form the central logic structure with easy access to all support and routing struc- tures. the iobs are located around all the logic and mem- ory elements for easy and quick routing of signals on and off the chip. values stored in static memory cells control all the config- urable logic elements and interconnect resources. these values load into the memory cells on power-up, and can reload if necessary to change the function of the device. each of these elements will be discussed in detail in the fol- lowing sections. input/output block the spartan-iie iob, as seen in figure 2 , features inputs and outputs that support a wide variety of i/o signaling stan- dards. these high-speed inputs and outputs are capable of supporting various state of the art memory and bus inter- faces. ta b l e 1 lists several of the standards which are sup- ported along with the required reference, output and termination voltages needed to meet the standard. the three iob registers function either as edge-triggered d-type flip-flops or as level-sensitive latches. each iob has a clock signal (clk) shared by the three registers and inde- pendent clock enable (ce) signals for each register. 020 spartan-iie 1.8v fpga family: functional description ds077-2 (v2.1) july 9, 2003 0 0 product specification r figure 1: basic spartan-iie family fpga block diagram dll dll dll dll block ram block ram block ram block ram i/o logic clbs clbs clbs clbs ds077_01_052102
spartan-iie 1.8v fpga family: functional description 2 www.xilinx.com ds077-2 (v2.1) july 9, 2003 1-800-255-7778 product specification r in addition to the clk and ce control signals, the three reg- isters share a set/reset (sr). for each register, this signal can be independently configured as a synchronous set, a synchronous reset, an asynchronous preset, or an asyn- chronous clear. a feature not shown in the block diagram, but controlled by the software, is polarity control. the input and output buffers and all of the iob control signals have independent polarity controls. optional pull-up and pull-down resistors and an optional weak-keeper circuit are attached to each user i/o pad. prior to configuration all outputs not involved in configuration are forced into their high-impedance state. the pull-down resis- tors and the weak-keeper circuits are inactive, but inputs may optionally be pulled up. the activation of pull-up resis- tors prior to configuration is controlled on a global basis by the configuration mode pins. if the pull-up resistors are not activated, all the pins will float. consequently, external pull-up or pull-down resistors must be provided on pins required to be at a well-defined logic level prior to configura- tion. all pads are protected against damage from electrostatic discharge (esd) and from over-voltage transients. after configuration, clamping diodes are connected to v cco for lvttl, pci, hstl, sstl, ctt, and agp standards. figure 2: spartan-iie input/output block (iob) package pin package pin package pin d ck ec sr q d ck ec sr q d ck ec sr q programmable bias and esd network v cco i/o i/o, v ref internal reference to next i/o to other external v ref inputs of bank notes: 1. for som e i/o standards. programmable input buffer programmable output buffer programmable delay v cc v cc (1) oe sr o oce i ice iq clk tce t ds077-2_01_051501 tff off iff table 1: standards supported by i/o (typical values) i/o standard input ref. volt. (v ref ) input volt. (v cco ) output source volt. (v cco ) board term. volt. (v tt ) lvttl (2-24 ma) n/a 3.3 3.3 n/a lv c m o s 2 n/a 2.5 2.5 n/a lv c m o s 1 8 n/a 1.8 1.8 n/a pci (3v, 33 mhz/66 mhz) n/a 3.3 3.3 n/a gtl 0.8 n/a n/a 1.2 gtl+ 1.0 n/a n/a 1.5 hstl class i 0.75 n/a 1.5 0.75 hstl class iii 0.9 n/a 1.5 1.5 hstl class iv 0.9 n/a 1.5 1.5 sstl3 class i and ii 1.5 n/a 3.3 1.5 sstl2 class i and ii 1.25 n/a 2.5 1.25 ctt 1.5 n/a 3.3 1.5 agp 1.32 n/a 3.3 n/a lv d s, b u s lv d s n/a n/a 2.5 n/a lvpecl n/a n/a 3.3 n/a
spartan-iie 1.8v fpga family: functional description ds077-2 (v2.1) july 9, 2003 www.xilinx.com 3 product specification 1-800-255-7778 r all spartan-iie iobs support ieee 1149.1-compatible boundary scan testing. input path a buffer in the spartan-iie iob input path routes the input signal directly to internal logic and through an optional input flip-flop. an optional delay element at the d-input of this flip-flop elim- inates pad-to-pad hold time. the delay is matched to the internal clock-distribution delay of the fpga, and when used, assures that the pad-to-pad hold time is zero. each input buffer can be configured to conform to any of the low-voltage signaling standards supported. in some of these standards the input buffer utilizes a user-supplied threshold voltage, v ref . the need to supply v ref imposes constraints on which standards can used in close proximity to each other. see i/o banking . there are optional pull-up and pull-down resistors at each input for use after configuration. output path the output path includes a 3-state output buffer that drives the output signal onto the pad. the output signal can be routed to the buffer directly from the internal logic or through an optional iob output flip-flop. the 3-state control of the output can also be routed directly from the internal logic or through a flip-flip that provides syn- chronous enable and disable. each output driver can be individually programmed for a wide range of low-voltage signaling standards. each output buffer can source up to 24 ma and sink up to 48 ma. drive strength and slew rate controls minimize bus transients. in most signaling standards, the output high voltage depends on an externally supplied v cco voltage. the need to supply v cco imposes constraints on which standards can be used in close proximity to each other. see i/o bank- ing . an optional weak-keeper circuit is connected to each out- put. when selected, the circuit monitors the voltage on the pad and weakly drives the pin high or low to match the input signal. if the pin is connected to a multiple-source sig- nal, the weak keeper holds the signal in its last state if all drivers are disabled. maintaining a valid logic level in this way helps eliminate bus chatter. because the weak-keeper circuit uses the iob input buffer to monitor the input level, an appropriate v ref voltage must be provided if the signaling standard requires one. the pro- vision of this voltage must comply with the i/o banking rules. i/o banking some of the i/o standards described above require v cco and/or v ref voltages. these voltages are externally sup- plied and connected to device pins that serve groups of iobs, called banks. consequently, restrictions exist about which i/o standards can be combined within a given bank. eight i/o banks result from separating each edge of the fpga into two banks (see figure 3 ). the pinout tables show the bank affiliation of each i/o (see pinout tables , module 4). each bank has multiple v cco pins which must be connected to the same voltage. voltage requirements are determined by the output standards in use. in the tq144 and pq208 packages, the eight banks have v cco connected together. thus, only one v cco level is allowed in these packages, although different v ref values are allowed in each of the eight banks. within a bank, standards may be mixed only if they use the same v cco . compatible standards are shown in ta b l e 2 . gtl and gtl+ appear under all voltages because their open-drain outputs do not depend on v cco . note that v cco is required for most output standards and for lvttl, lvcmos, and pci inputs. some input standards require a user-supplied threshold voltage, v ref . in this case, certain user-i/o pins are auto- matically configured as inputs for the v ref voltage. about one in six of the i/o pins in the bank assume this role. figure 3: spartan-iie i/o banks ta b l e 2 : compatible standards v cco compatible standards 3.3v pci, lvttl, sstl3 i, sstl3 ii, ctt, agp, lvpecl, gtl, gtl+ 2.5v sstl2 i, sstl2 ii, lvcmos2, lvds, bus lvds, gtl, gtl+ 1.8v lvcmos18, gtl, gtl+ 1.5v hstl i, hstl iii, hstl iv, gtl, gtl+ ds077-2_02_051501 bank 0 gclk3 gclk2 gclk1 gclk0 bank 1 bank 5 bank 4 spartan-iie device bank 7 bank 6 bank 2 bank 3
spartan-iie 1.8v fpga family: functional description 4 www.xilinx.com ds077-2 (v2.1) july 9, 2003 1-800-255-7778 product specification r v ref pins within a bank are interconnected internally and consequently only one v ref voltage can be used within each bank. all v ref pins in the bank, however, must be con- nected to the external voltage source for correct operation. in a bank, inputs requiring v ref can be mixed with those that do not but only one v ref voltage may be used within a bank. the v cco and v ref pins for each bank appear in the device pinout tables. within a given package, the number of v ref and v cco pins can vary depending on the size of device. in larger devices, more i/o pins convert to v ref pins. since these are always a superset of the v ref pins used for smaller devices, it is possible to design a pcb that permits migration to a larger device. all v ref pins for the largest device anticipated must be connected to the v ref voltage, and not used for i/o. see xilinx application note xapp179 for more information on i/o resources. hot swap, hot insertion, hot socketing support the i/o pins support hot swap ? also called hot insertion and hot socketing ? and are considered compactpci friendly according to the pci bus v2.2 specification. con- sequently, an unpowered spartan-iie fpga can be plugged directly into a powered system or backplane with- out affecting or damaging the system or the fpga. the hot swap functionality is built into every xc2s150e, xc2s400e, and xc2s600e device. all other spartan-iie devices built after product change notice pcn2002-05 also include hot swap functionality. to support hot swap, spartan-iie devices include the follow- ing i/o features. signals can be applied to spartan-iie i/o pins before powering the fpga?s v ccint or v cco supply inputs. spartan-iie i/o pins are high-impedance (i.e., three-stated) before and throughout the power-up and configuration processes when employing a configuration mode that does not enable the preconfiguration weak pull-up resistors (see ta b l e 9 , page 13 ). there is no current path from the i/o pin back to the v ccint or v cco voltage supplies. spartan-iie fpgas are immune to latch-up during hot swap. once connected to the system, each pin adds a small amount of capacitance (c in ). likewise, each i/o consumes a small amount of dc current, equivalent to the input leak- age specification (i l ). there also may be a small amount of temporary ac current (i hspo ) when the pin input voltage exceeds v cco plus 0.4v, which lasts less than 10 ns. a weak-keeper circuit within each user-i/o pin is enabled during the last frame of configuration data and has no noticeable effect on robust system signals driven by an active driver or a strong pull-up or pull-down resistor. undriven or floating system signals may be affected. the specific effect depends on how the i/o pin is configured. user-i/o pins configured as outputs or enabled outputs have a weak pull-up resistor to v cco during the last config- uration frame. user-i/o pins configured as inputs or bidirec- tional i/os have weak pull-down resistors. the weak-keeper circuit turns off when the done pin goes high, provided that it is not used in the configured application. configurable logic block the basic building block of the spartan-iie clb is the logic cell (lc). an lc includes a 4-input function generator, carry logic, and storage element. the output from the function generator in each lc drives the clb output or the d input of the flip-flop. each spartan-iie clb contains four lcs, orga- nized in two similar slices; a single slice is shown in figure 4 . in addition to the four basic lcs, the spartan-iie clb con- tains logic that combines function generators to provide functions of five or six inputs. look-up tables spartan-iie function generators are implemented as 4-input look-up tables (luts). in addition to operating as a function generator, each lut can provide a 16 x 1-bit synchronous ram. furthermore, the two luts within a slice can be com- bined to create a 16 x 2-bit or 32 x 1-bit synchronous ram, or a 16 x 1-bit dual-port synchronous ram. the spartan-iie lut can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. this mode can also be used to store data in applications such as digital signal processing. storage elements storage elements in the spartan-iie slice can be configured either as edge-triggered d-type flip-flops or as level-sensi- tive latches. the d inputs can be driven either by function generators within the slice or directly from slice inputs, bypassing the function generators. in addition to clock and clock enable signals, each slice has synchronous set and reset signals (sr and by). sr forces a storage element into the initialization state speci- fied for it in the configuration. by forces it into the opposite state. alternatively, these signals may be configured to operate asynchronously. all control signals are independently invertible, and are shared by the two flip-flops within the slice. table 3: i/o banking package tq144, pq208 ft256, fg456, fg676 v cco banks interconnected as 1 8 independent v ref banks 8 independent 8 independent
spartan-iie 1.8v fpga family: functional description ds077-2 (v2.1) july 9, 2003 www.xilinx.com 5 product specification 1-800-255-7778 r additional logic the f5 multiplexer in each slice combines the function gen- erator outputs ( figure 5 ). this combination provides either a function generator that can implement any 5-input func- tion, a 4:1 multiplexer, or selected functions of up to nine inputs. similarly, the f6 multiplexer combines the outputs of all four function generators in the clb by selecting one of the two f5-multiplexer outputs. this permits the implementation of any 6-input function, an 8:1 multiplexer, or selected func- tions of up to 19 inputs. figure 4: spartan-iie clb slice (two identical slices in each clb) i3 i4 i2 i1 look-up table d ck ec q r s i3 i4 i2 i1 o o look-up table d ck ec q r s xq x xb ce clk cin bx f1 f2 f3 sr by f5in g1 g2 yq y yb cout g3 g4 f4 carry and control logic carry and control logic ds001_04_091400
spartan-iie 1.8v fpga family: functional description 6 www.xilinx.com ds077-2 (v2.1) july 9, 2003 1-800-255-7778 product specification r each clb has four direct feedthrough paths, one per lc. these paths provide extra data input lines or additional local routing that does not consume logic resources. arithmetic logic dedicated carry logic provides fast arithmetic carry capabil- ity for high-speed arithmetic functions. the spartan-iie clb supports two separate carry chains, one per slice. the height of the carry chains is two bits per clb. the arithmetic logic includes an xor gate that allows a 1-bit full adder to be implemented within an lc. in addition, a dedicated and gate improves the efficiency of multiplier implementations. the dedicated carry path can also be used to cascade func- tion generators for implementing wide logic functions. bufts each spartan-iie clb contains two 3-state drivers (bufts) that can drive on-chip busses. the iobs on the left and right sides can also drive the on-chip busses. see dedicated routing , page 8 . each spartan-iie buft has an indepen- dent 3-state control pin and an independent input pin. the 3-state control pin is an active-low enable (t). when all bufts on a net are disabled, the net is high. there is no need to instantiate a pull-up unless desired for simulation purposes. simultaneously driving bufts onto the same net will not cause contention. if driven both high and low, the net will be low. block ram spartan-iie fpgas incorporate several large block ram memories. these complement the distributed ram look-up tables (luts) that provide shallow memory struc- tures implemented in clbs. block ram memory blocks are organized in columns. most spartan-iie devices contain two such columns, one along each vertical edge. the xc2s400e has four block ram col- umns and the xc2s600e has six block ram columns. these columns extend the full height of the chip. each memory block is four clbs high, and consequently, a spartan-iie device 16 clbs high will contain four memory blocks per column, and a total of eight blocks. each block ram cell, as illustrated in figure 6 , is a fully syn- chronous dual-ported 4096-bit ram with independent con- trol signals for each port. the data widths of the two ports can be configured independently, providing built-in bus-width conversion. figure 5: f5 and f6 multiplexers lut ds077-2_05-111501 lut muxf5 muxf6 lut slice slice clb lut muxf5 ta b l e 4 : spartan-iie block ram amounts spartan-iie device # of blocks total block ram bits xc2s50e 8 32k xc2s100e 10 40k xc2s150e 12 48k XC2S200E 14 56k xc2s300e 16 64k xc2s400e 40 160k xc2s600e 72 288k figure 6: dual-port block ram web enb rstb clkb addrb[#:0] dib[#:0] wea ena rsta clka add[#:0] dia[#:0] doa[#:0] dob[#:0] ramb4_s#_s# ds001_05_060100
spartan-iie 1.8v fpga family: functional description ds077-2 (v2.1) july 9, 2003 www.xilinx.com 7 product specification 1-800-255-7778 r ta b l e 5 shows the depth and width aspect ratios for the block ram. the spartan-iie block ram also includes dedicated routing to provide an efficient interface with both clbs and other block rams. see xilinx application note xapp173 for more information on block ram. programmable routing it is the longest delay path that limits the speed of any design. consequently, the spartan-iie routing architecture and its place-and-route software were defined jointly to min- imize long-path delays and yield the best system perfor- mance. the joint optimization also reduces design compilation times because the architecture is software-friendly. design cycles are correspondingly reduced due to shorter design iteration times. the software automatically uses the best available routing based on user timing requirements. the details are pro- vided here for reference. local routing the local routing resources, as shown in figure 7 , provide the following three types of connections: interconnections among the luts, flip-flops, and general routing matrix (grm), described below. internal clb feedback paths that provide high-speed connections to luts within the same clb, chaining them together with minimal routing delay direct paths that provide high-speed connections between horizontally adjacent clbs, eliminating the delay of the grm general purpose routing most spartan-iie signals are routed on the general purpose routing, and consequently, the majority of interconnect resources are associated with this level of the routing hier- archy. the general routing resources are located in horizon- tal and vertical routing channels associated with the rows and columns of clbs. the general-purpose routing resources are listed below. adjacent to each clb is a general routing matrix (grm). the grm is the switch matrix through which horizontal and vertical routing resources connect, and is also the means by which the clb gains access to the general purpose routing. 24 single-length lines route grm signals to adjacent grms in each of the four directions. 96 buffered hex lines route grm signals to other grms six blocks away in each one of the four directions. organized in a staggered pattern, hex lines may be driven only at their endpoints. hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). one third of the hex lines are bidirectional, while the remaining ones are unidirectional. 12 longlines are buffered, bidirectional wires that distribute signals across the device quickly and efficiently. vertical longlines span the full height of the device, and horizontal ones span the full width of the device. i/o routing spartan-iie devices have additional routing resources around their periphery that form an interface between the clb array and the iobs. this additional routing, called the versaring? routing, facilitates pin-swapping and pin-lock- ing, such that logic redesigns can adapt to existing pcb lay- outs. time-to-market is reduced, since pcbs and other system components can be manufactured while the logic design is still in progress. table 5: block ram port aspect ratios width depth addr bus data bus 1 4096 addr<11:0> data<0> 2 2048 addr<10:0> data<1:0> 4 1024 addr<9:0> data<3:0> 8 512 addr<8:0> data<7:0> 16 256 addr<7:0> data<15:0> figure 7: spartan-iie local routing ds001_06_032300 clb grm to adjacent grm to adjacent grm direct connection to adjacent clb to adjacent grm to adjacent grm direct connection to adjacent clb
spartan-iie 1.8v fpga family: functional description 8 www.xilinx.com ds077-2 (v2.1) july 9, 2003 1-800-255-7778 product specification r dedicated routing some classes of signal require dedicated routing resources to maximize performance. in the spartan-iie architecture, dedicated routing resources are provided for two classes of signal. horizontal routing resources are provided for on-chip 3-state busses. four partitionable bus lines are provided per clb row, permitting multiple busses within a row, as shown in figure 8 . two dedicated nets per clb propagate carry signals vertically to the adjacent clb. global routing global routing resources distribute clocks and other sig- nals with very high fanout throughout the device. spar- tan-iie devices include two tiers of global routing resources referred to as primary and secondary global routing resources. the primary global routing resources are four dedicated global nets with dedicated input pins that are designed to distribute high-fanout clock signals with minimal skew. each global clock net can drive all clb, iob, and block ram clock pins. the primary global nets may only be driven by global buffers. there are four global buffers, one for each global net. the secondary global routing resources consist of 24 backbone lines, 12 across the top of the chip and 12 across the bottom. from these lines, up to 12 unique signals per column can be distributed via the 12 longlines in the column. these secondary resources are more flexible than the primary resources since they are not restricted to routing only to clock pins. clock distribution the spartan-iie family provides high-speed, low-skew clock distribution through the primary global routing resources described above. a typical clock distribution net is shown in figure 9 . four global buffers are provided, two at the top center of the device and two at the bottom center. these drive the four primary global nets that in turn drive any clock pin. four dedicated clock pads are provided, one adjacent to each of the global buffers. the input to the global buffer is selected either from these pads or from signals in the gen- eral purpose routing. delay-locked loop (dll) associated with each global clock input buffer is a fully digi- tal delay-locked loop (dll) that can eliminate skew between the clock input pad and internal clock-input pins throughout the device. each dll can drive two global clock networks. the dll monitors the input clock and the distrib- uted clock, and automatically adjusts a clock delay element ( figure 10 ). additional delay is introduced such that clock edges reach internal flip-flops exactly one clock period after they arrive at the input. this closed-loop system effectively eliminates clock-distribution delay by ensuring that clock figure 8: buft connections to dedicated horizontal bus lines clb clb clb clb 3-state lines ds001_07_090600 figure 9: global clock distribution network global clock spine global clock column gclkpad2 gclkbuf2 gclkpad3 gclkbuf3 gclkbuf1 gclkpad1 gclkbuf0 gclkpad0 global clock rows ds001_08_060100
spartan-iie 1.8v fpga family: functional description ds077-2 (v2.1) july 9, 2003 www.xilinx.com 9 product specification 1-800-255-7778 r edges arrive at internal flip-flops in synchronism with clock edges arriving at the input. in addition to eliminating clock-distribution delay, the dll provides advanced control of multiple clock domains. the dll provides four quadrature phases of the source clock, can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16. the phase-shifted output have optional duty-cycle correction ( figure 11 ). the dll also operates as a clock mirror. by driving the out- put from a dll off-chip and then back on again, the dll can be used to deskew a board level clock among multiple spar- tan-iie devices. in order to guarantee that the system clock is operating cor- rectly prior to the fpga starting up after configuration, the dll can delay the completion of the configuration process until after it has achieved lock. if the dll uses external feed- back, apply a reset after startup to ensure consistent lock- ing to the external signal. see xilinx application note xapp174 for more information on dlls. boundary scan spartan-iie devices support all the mandatory bound- ary-scan instructions specified in the ieee standard 1149.1. a test access port (tap) and registers are provided that implement the extest, intest, sample/preload, bypass, idcode, and highz instructions. the tap also supports two usercode instructions, internal scan chains, and configuration/readback of the device. the tap uses dedicated package pins that always operate using lvttl. for tdo to operate using lvttl, the v cco for bank 2 must be 3.3v. otherwise, tdo switches rail-to-rail between ground and v cco . the boundary-scan input pins (tdi, tms, tck) do not have a v cco requirement and oper- ate with either 2.5v or 3.3v input signalling levels. boundary-scan operation is independent of individual iob configurations, and unaffected by package type. all iobs, including unbonded ones, are treated as independent 3-state bidirectional pins in a single scan chain. retention of the bidirectional test capability after configuration facilitates the testing of external interconnections. ta b l e 6 lists the boundary-scan instructions supported in spartan-iie fpgas. internal signals can be captured during extest by connecting them to unbonded or unused iobs. they may also be connected to the unused outputs of iobs defined as unidirectional input pins. figure 10: delay-locked loop block diagram figure 11: dll output characteristics clock distribution network variable delay line clkout control clkfb clkin ds077-2_10_070203 x132_07_092599 clkin clk2x clk0 clk90 clk180 clk270 clkdv clkdv_divide=2 duty_cycle_correction=false clk0 clk90 clk180 clk270 duty_cycle_correction=true t 0 90 180 270 0 90 180 270 ta b l e 6 : boundary-scan instructions boundary-scan command binary code[4:0] description extest 00000 enables boundary-scan extest operation sample/ preload 00001 enables boundary-scan sample/preload operation user1 00010 access user-defined register 1 user2 00011 access user-defined register 2 cfg_out 00100 access the configuration bus for readback cfg_in 00101 access the configuration bus for configuration intest 00111 enables boundary-scan intest operation
spartan-iie 1.8v fpga family: functional description 10 www.xilinx.com ds077-2 (v2.1) july 9, 2003 1-800-255-7778 product specification r the public boundary-scan instructions are available prior to configuration, except for user1 and user2. after configu- ration, the public instructions remain available together with any usercode instructions installed during the configura- tion. while the sample/preload and bypass instruc- tions are available during configuration, it is recommended that boundary-scan operations not be performed during this transitional period. in addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the fpga, and also to read back the configuration data. to facilitate internal scan chains, the user register provides three outputs (reset, update, and shift) that represent the corresponding states in the boundary-scan internal state machine. figure 12 is a diagram of the spartan-iie family boundary scan logic. it includes three bits of data register per iob, the ieee 1149.1 test access port controller, and the instruction register with decodes. usercode 01000 enables shifting out user code idcode 01001 enables shifting out of id code highz 01010 disables output pins while enabling the bypass register jstart 01100 clock the start-up sequence when startupclk is tck bypass 11111 enables bypass reserved all other codes xilinx reserved instructions table 6: boundary-scan instructions (continued) boundary-scan command binary code[4:0] description figure 12: spartan-iie family boundary scan logic d q d q iob iob iob iob iob iob iob iob iob iob iob iob iob m u x bypass register iob iob tdo tdi iob iob iob 1 0 1 0 1 0 1 0 1 0 sd le dq d q d q 1 0 1 0 1 0 1 0 dq le sd sd le dq sd le dq iob d q 1 0 dq le sd iob.t data in iob.i iob.q iob.t iob.i shift/ capture clock data register dataout update extest ds001_09_032300 instruction register
spartan-iie 1.8v fpga family: functional description ds077-2 (v2.1) july 9, 2003 www.xilinx.com 11 product specification 1-800-255-7778 r bit sequence the bit sequence within each iob is: in, out, 3-state. the input-only pins contribute only the in bit to the boundary scan i/o data register, while the output-only pins contributes all three bits. from a cavity-up view of the chip (as shown in the fpga editor), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in figure 13 . bsdl (boundary scan description language) files for spartan-iie family devices are available on the xilinx web site at http://www.xilinx.com/support/sw_bsdl.htm . spartan-iie boundary scan idcode values are shown in ta b l e 7 . development system spartan-iie fpgas are supported by the xilinx ise foun- dation and alliance cae tools. the basic methodology for spartan-iie design consists of three interrelated steps: design entry, implementation, and verification. industry-standard tools are used for design entry and simu- lation, while xilinx provides proprietary architecture-specific tools for implementation. the xilinx development system is integrated under the xilinx project navigator software, providing designers with a common user interface regardless of their choice of entry and verification tools. the software simplifies the selection of implementation options with pull-down menus and on-line help. application programs ranging from schematic capture to placement and routing can be accessed through the soft- ware. the program command sequence is generated prior to execution, and stored for documentation. several advanced software features facilitate spartan-iie design. core generator? functions, for example, include macros with relative location constraints to guide their placement. they help ensure optimal implementation of common functions. for hdl design entry, the xilinx fpga development system provides interfaces to several synthesis design environ- ments. a standard interface-file specification, electronic design interchange format (edif), simplifies file transfers into and out of the development system. spartan-iie fpgas are supported by a unified library of standard functions. this library contains over 400 primitives and macros, ranging from 2-input and gates to 16-bit accu- mulators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, i/o functions, latches, boolean functions, multiplexers, shift registers, and barrel shifters. figure 13: boundary scan bit sequence bit 0 ( tdo end) bit 1 bit 2 tdo.t tdo.o top-edge iobs (right to left) left-edge iobs (top to bottom) mode.i bottom-edge iobs (left to right) right-edge iobs (bottom to top) bscant.upd (tdi end) ds001_10_032300 table 7: spartan-iie idcode values device idcode version family array size manufacturer required xc2s50e xxxx 0000 101 0 0001 0000 0000 1001 001 1 xc2s100e xxxx 0000 101 0 0001 0100 0000 1001 001 1 xc2s150e xxxx 0000 101 0 0001 1000 0000 1001 001 1 XC2S200E xxxx 0000 101 0 0001 1100 0000 1001 001 1 xc2s300e xxxx 0000 101 0 0010 0000 0000 1001 001 1 xc2s400e xxxx 0000 101 0 0010 1000 0000 1001 001 1 xc2s600e xxxx 0000 101 0 0011 0000 0000 1001 001 1
spartan-iie 1.8v fpga family: functional description 12 www.xilinx.com ds077-2 (v2.1) july 9, 2003 1-800-255-7778 product specification r the design environment supports hierarchical design entry, with high-level designs that comprise major functional blocks, while lower-level designs define the logic in these blocks. these hierarchical design elements are automati- cally combined by the implementation tools. different design entry tools can be combined within a hierarchical design, thus allowing the most convenient entry method to be used for each portion of the design. design implementation the place-and-route tools automatically provide the imple- mentation flow described in this section. the partitioner takes the edif netlist for the design and maps the logic into the architectural resources of the fpga (clbs and iobs, for example). the placer then determines the best locations for these blocks based on their interconnections and the desired performance. finally, the router interconnects the blocks. the algorithms support fully automatic implementation of most designs. for demanding applications, however, the user can exercise various degrees of control over the pro- cess. user partitioning, placement, and routing information is optionally specified during the design-entry process. the implementation of highly structured designs can benefit greatly from basic floorplanning. the implementation software incorporates timing-driven placement and routing. designers specify timing require- ments along entire paths during design entry. the timing path analysis routines then recognize these user-specified requirements and accommodate them. timing requirements are entered in a form directly relating to the system requirements, such as the targeted clock fre- quency, or the maximum allowable delay between two reg- isters. in this way, the overall performance of the system along entire signal paths is automatically tailored to user-generated specifications. specific timing information for individual nets is unnecessary. design verification in addition to conventional software simulation, fpga users can use in-circuit debugging techniques. because xilinx devices are infinitely reprogrammable, designs can be veri- fied in real time without the need for extensive sets of soft- ware simulation vectors. the development system supports both software simulation and in-circuit debugging techniques. for simulation, the system extracts the post-layout timing information from the design database, and back-annotates this information into the netlist for use by the simulator. alternatively, the user can verify timing-critical portions of the design using the static timing analyzer. for in-circuit debugging, xilinx offers a download and read- back cable, which connects the fpga in the target system to a pc or workstation. after downloading the design into the fpga, the designer can single-step the logic, readback the contents of the flip-flops, and so observe the internal logic state. simple modifications can be downloaded into the system in a matter of minutes. configuration configuration is the process by which the bitstream of a design, as generated by the xilinx development software, is loaded into the internal configuration memory of the fpga. spartan-iie devices support both serial configuration, using the master/slave serial and jtag modes, as well as byte-wide configuration employing the slave parallel mode. configuration file spartan-iie devices are configured by sequentially loading frames of data that have been concatenated into a configu- ration file. ta b l e 8 shows how much nonvolatile storage space is needed for spartan-iie devices. it is important to note that, while a prom is commonly used to store configuration data before loading them into the fpga, it is by no means required. any of a number of differ- ent kinds of under populated nonvolatile storage already available either on or off the board (for example, hard drives, flash cards, and so on) can be used. modes spartan-iie devices support the following four configuration modes: slave serial mode master serial mode slave parallel mode boundary-scan mode the configuration mode pins (m2, m1, m0) select among these configuration modes with the option in each case of having the iob pins either pulled up or left floating prior to configuration. the selection codes are listed in ta b l e 9 . configuration through the boundary-scan port is always available, independent of the mode selection. selecting the boundary-scan mode simply turns off the other modes. the three mode pins have internal pull-up resistors, and default to a logic high if left unconnected. ta b l e 8 : spartan-iie configuration file size device configuration file size (bits) xc2s50e 630,048 xc2s100e 863,840 xc2s150e 1,134,496 XC2S200E 1,442,016 xc2s300e 1,875,648 xc2s400e 2,693,440 xc2s600e 3,961,632
spartan-iie 1.8v fpga family: functional description ds077-2 (v2.1) july 9, 2003 www.xilinx.com 13 product specification 1-800-255-7778 r signals there are two kinds of pins that are used to configure spartan-iie devices: dedicated pins perform only specific configuration-related functions; the other pins can serve as general purpose i/os once user operation has begun. the dedicated pins comprise the mode pins (m2, m1, m0), the configuration clock pin (cclk), the program pin, the done pin and the boundary-scan pins (tdi, tdo, tms, tck). depending on the selected configuration mode, cclk may be an output generated by the fpga, or may be generated externally, and provided to the fpga as an input. note that some configuration pins can act as outputs. for correct operation, these pins require a v cco of 3.3v to drive an lvttl signal or 2.5v to drive an lvcmos signal. all the relevant pins fall in banks 2 or 3. the cs and write pins for slave parallel mode are located in bank 1. for a more detailed description than that given below, see spartan-iie 1.8v fpga family: pinout tables and xapp176 , spartan-ii fpga series configuration and readback . the process the sequence of steps necessary to configure spartan-iie devices are shown in figure 14 . the overall flow can be divided into three different phases. initiating configuration configuration memory clear loading data frames start-up the memory clearing and start-up phases are the same for all configuration modes; however, the steps for the loading of data frames are different. thus, the details for data frame loading are described separately in the sections devoted to each mode. initiating configuration there are two different ways to initiate the configuration pro- cess: applying power to the device or asserting the pro- gram input. configuration on power-up occurs automatically unless it is delayed by the user, as described in a separate section below. the waveform for configuration on power-up is shown in spartan-iie 1.8v fpga family: dc and switch- ing characteristics . before configuration can begin, v cco bank 2 must be greater than 1.0v. furthermore, all v ccint power pins must be connected to a 1.8v supply. for more information on delaying configuration, see clearing con- figuration memory , page 14 . once in user operation, the device can be re-configured simply by pulling the program pin low. the device acknowledges the beginning of the configuration process by driving done low, then enters the memory-clearing phase. table 9: configuration modes configuration mode preconfiguration pull-ups m0 m1 m2 cclk direction data width serial d out master serial mode no 0 0 0 out 1 ye s ye s 0 0 1 slave parallel mode (selectmap) ye s 0 1 0 in 8 no no 0 1 1 boundary-scan mode ye s 1 0 0 n/a 1 no no 1 0 1 slave serial mode ye s 1 1 0 in 1 ye s no 1 1 1
spartan-iie 1.8v fpga family: functional description 14 www.xilinx.com ds077-2 (v2.1) july 9, 2003 1-800-255-7778 product specification r clearing configuration memory the device indicates that clearing the configuration memory is in progress by driving init low. delaying configuration at this time, the user can delay configuration by holding either program or init low, which causes the device to remain in the memory clearing phase. note that the bidirec- tional init line is driving a low logic level during memory clearing. thus, to avoid contention, use an open-drain driver to keep init low. with no delay in force, the device indicates that the memory is completely clear by driving init high. the fpga samples its mode pins on this low-to-high transition. loading configuration data once init is high, the user can begin loading configuration data frames into the device. the details of loading the con- figuration data are discussed in the sections treating the configuration modes individually. the sequence of opera- tions necessary to load configuration data using the serial modes is shown in figure 16 . loading data using the slave parallel mode is shown in figure 19, page 19 . crc error checking after the loading of configuration data, a crc value embed- ded in the configuration file is checked against a crc value calculated within the fpga. if the crc values do not match, the fpga drives init low to indicate that an error has occurred and configuration is aborted. note that attempting to load an incorrect bitstream causes configura- tion to fail and can damage the device. to reconfigure the device, the program pin should be asserted to reset the configuration logic. recycling power also resets the fpga for configuration. see clearing con- figuration memory . start-up the start-up sequence oversees the transition of the fpga from the configuration state to full user operation. a match of crc values, indicating a successful loading of the config- uration data, initiates the sequence. figure 14: configuration flow diagram fpga drives init low abort start-up user holding init low? user holding program low? fpga drives init and done low load configuration data frames user operation configuration at power-up ds001_11_111501 no crc correct? yes fpga samples mode pins delay configuration delay configuration clear configuration memory user pulls program low start-up sequence fpga drives done high, activates i/os, releases gsr net yes no yes no no yes configuration during user operation v cco and v ccint high?
spartan-iie 1.8v fpga family: functional description ds077-2 (v2.1) july 9, 2003 www.xilinx.com 15 product specification 1-800-255-7778 r during start-up, the device performs four operations: 1. the assertion of done. the failure of done to go high may indicate the unsuccessful loading of configuration data. 2. the release of the global three state (gts). this activates all the i/os. 3. the release of the global set reset (gsr). this allows all flip-flops to change state. 4. the assertion of global write enable (gwe). this allows all rams and flip-flops to change state. by default, these operations are synchronized to cclk. the entire start-up sequence lasts eight cycles, called c0-c7, after which the loaded design is fully functional. the four operations can be selected to switch on any cclk cycle c1-c6 through settings in the xilinx development software. the default timing for start-up is shown in the top half of figure 15 ; heavy lines show default settings. the default start-up sequence is that one cclk cycle after done goes high, the global 3-state signal (gts) is released. this permits device outputs to turn on as neces- sary. one cclk cycle later, the global set/reset (gsr) and glo- bal write enable (gwe) signals are released. this permits the internal storage elements to begin changing state in response to the logic and the user clock. the bottom half of figure 15 shows another commonly used version of the start-up timing known as sync-to-done. this version makes the gts, gsr, and gwe events conditional upon the done pin going high. this timing is important for a daisy chain of multiple fpgas in serial mode, since it ensures that all fpgas go through start-up together, after all their done pins have gone high. sync-to-done timing is selected by setting the gts, gsr, and gwe cycles to a value of done in the configuration options. this causes these signals to transition one clock cycle after done externally transitions high. the sequence can also be paused at any stage until lock has been achieved on any or all dlls. serial modes there are two serial configuration modes. in master serial mode, the fpga controls the configuration process by driv- ing cclk as an output. in slave serial mode, the fpga passively receives cclk as an input from an external agent (e.g., a microprocessor, cpld, or second fpga in master mode) that is controlling the configuration process. in both modes, the fpga is configured by loading one bit per cclk cycle. the msb of each configuration data byte is always written to the din pin first. see figure 16 for the sequence for loading data into the spartan-iie fpga serially. this is an expansion of the "load configuration data frames" block in figure 14, page 14 . figure 15: start-up waveforms start-up clk default cycles sync to done 0123 4567 01 done high 23 4567 phase start-up clk phase done gts gsr gwe ds001_13_090600 done gts gsr gwe
spartan-iie 1.8v fpga family: functional description 16 www.xilinx.com ds077-2 (v2.1) july 9, 2003 1-800-255-7778 product specification r slave serial mode in slave serial mode, the fpga?s cclk pin is driven by an external source, allowing the fpga to be configured from other logic devices such as microprocessors or in a daisy-chain configuration. figure 17 shows connections for a master serial fpga configuring a slave serial fpga from a prom. a spartan-iie device in slave serial mode should be connected as shown for the third device from the left. slave serial mode is selected by a <11x> on the mode pins (m0, m1, m2). the weak pull-ups on the mode pins make slave serial the default mode if the pins are left uncon- nected. the serial bitstream must be setup at the din input pin a short time before each rising edge of an externally gener- ated cclk. timing for slave serial mode is shown in spartan-iie 1.8v fpga family: dc and switching characteristics . daisy chain multiple fpgas in slave serial mode can be daisy-chained for configuration from a single source. after an fpga is configured, data for the next device is sent to the dout pin. data on the dout pin changes on the rising edge of cclk. note that dout changes on the falling edge of cclk for some xilinx families but mixed daisy chains are allowed. configuration must be delayed until init pins of all daisy-chained fpgas are high. for more information, see start-up , page 14 . figure 16: loading serial mode configuration data no yes end of configuration data file? after init goes high user load one configuration bit on next cclk rising edge to crc check ds001_14_032300 notes: 1. if the drivedone configuration option is not active for any of the fpgas, pull up done with a 3.3k ? resistor or lower. figure 17: master/slave serial configuration circuit diagram spartan-iie (master serial) xilinx prom program m2 m0 m1 dout cclk clk 3.3v data ce ceo reset/oe din init done program 3.3 k ds077-2_04_070203 gnd gnd v cc 3.3v v cco v ccint 1.8v 3.3v 3.3v 1.8v spartan-iie (slave) done init program cclk din dout m2 m0 m1 gnd v cco v ccint
spartan-iie 1.8v fpga family: functional description ds077-2 (v2.1) july 9, 2003 www.xilinx.com 17 product specification 1-800-255-7778 r master serial mode in master serial mode, the cclk output of the fpga drives a xilinx prom, which feeds a serial stream of configuration data to the fpga?s din input. figure 17 shows a master serial fpga configuring a slave serial fpga from a prom. a spartan-iie device in master serial mode should be connected as shown for the device on the left side. mas- ter serial mode is selected by a <00x> on the mode pins (m0, m1, m2). the prom reset pin is driven by init , and the ce input is driven by done. for more information on serial proms, see the xilinx configuration prom data sheets at: http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp . the interface is identical to the slave serial mode except that an oscillator internal to the fpga is used to generate the configuration clock (cclk). any of a number of different frequencies ranging from 4 to 60 mhz can be set using the configrate option in the xilinx development software. when selecting a cclk frequency, ensure that the serial prom and any daisy-chained fpgas are fast enough to support the clock rate. on power-up, while the first 60 bytes of the configuration data are being loaded, the cclk fre- quency is always 2.5 mhz. this frequency is used until the configrate bits, part of the configuration file, have been loaded into the fpga, at which point the frequency changes to the selected configrate. unless a different fre- quency is specified in the design, the default configrate is 4mhz. the fpga accepts one bit of configuration data on each ris- ing cclk edge. after the fpga has been loaded, the data for the next device in a daisy-chain is presented on the dout pin after the rising cclk edge. the timing for master serial mode is shown in spartan-iie 1.8v fpga family: dc and switching characteristics . slave parallel mode (selectmap) the slave parallel mode, also known as selectmap, is the fastest configuration option. byte-wide data is written into the fpga on the d0-d7 pins. note that d0 is the msb of each byte for configuration. a busy flag is provided for con- trolling the flow of data at a clock frequency above 50 mhz. figure 18, page 18 shows the connections for two spartan-iie devices using the slave parallel mode. slave parallel mode is selected by a <011> on the mode pins (m0, m1, m2). the agent controlling configuration is not shown. typically, a processor, a microcontroller, or cpld controls the slave parallel interface. the controlling agent provides byte-wide configuration data, cclk, a chip select (cs ) signal and a write signal (write ). if busy is asserted (high) by the fpga, the data must be held until busy goes low. after configuration, the pins of the slave parallel port (d0-d7) can be used as additional user i/o. alternatively, the port may be retained to permit high-speed 8-bit read- back. then data can be read by deasserting write . if retention is selected, prohibit the d0-d7 pins from being used as user i/o. see readback , page 19 .
spartan-iie 1.8v fpga family: functional description 18 www.xilinx.com ds077-2 (v2.1) july 9, 2003 1-800-255-7778 product specification r multiple spartan-iie fpgas can be configured using the slave parallel mode, and be made to start-up simulta- neously. to configure multiple devices in this way, wire the individual cclk, data, write , and busy pins of all the devices in parallel. the individual devices are loaded sepa- rately by asserting the cs pin of each device in turn and writing the appropriate data. sync-to-done start-up timing is used to ensure that the start-up sequence does not begin until all the fpgas have been loaded. see start-up , page 14 . write when using the slave parallel mode, write operations send packets of byte-wide configuration data into the fpga. figure 19, page 19 shows a flowchart of the write sequence used to load data into the spartan-iie fpga. this is an expansion of the "load configuration data frames" block in figure 14, page 14 . the timing for slave parallel mode is shown in spartan-iie 1.8v fpga family: dc and switching characteristics . for the present example, the user holds write and cs low throughout the sequence of write operations. note that when cs is asserted on successive cclks, write must remain either asserted or deasserted. otherwise an abort will be initiated, as in the next section. 1. drive data onto d0-d7. note that to avoid contention, the data source should not be enabled while cs is low and write is high. similarly, while write is high, no more than one device?s cs should be asserted. 2. on the rising edge of cclk: if busy is low, the data is accepted on this clock. if busy is high (from a previous write), the data is not accepted. acceptance will instead occur on the first clock after busy goes low, and the data must be held until this happens. 3. repeat steps 1 and 2 until all the data has been sent. 4. deassert cs and write . figure 18: slave parallel configuration circuit diagram m1 m2 m0 d0:d7 cclk write busy cs program done init cclk data[7:0] write busy cs(0) spartan-iie done init program m1 m2 m0 d0:d7 cclk write busy cs program done init cs(1) spartan-iie ds077-2_06_110102 gnd gnd
spartan-iie 1.8v fpga family: functional description ds077-2 (v2.1) july 9, 2003 www.xilinx.com 19 product specification 1-800-255-7778 r if cclk is slower than f ccnh , the fpga will never assert busy. in this case, the above handshake is unnecessary, and data can simply be entered into the fpga every cclk cycle. a configuration packet does not have to be written in one continuous stretch, rather it can be split into many write sequences. each sequence would involve assertion of cs . in applications where multiple clock cycles may be required to access the configuration data before each byte can be loaded into the slave parallel interface, a new byte of data may not be ready for each consecutive cclk edge. in such a case the cs signal may be deasserted until the next byte is valid on d0-d7. while cs is high, the slave parallel inter- face does not expect any data and ignores all cclk transi- tions. however, to avoid aborting configuration, write must continue to be asserted while cs is asserted during cclk transitions. abort to abort configuration during a write sequence, deassert write while holding cs low. the abort operation is initi- ated at the rising edge of cclk. the device will remain busy until the aborted operation is complete. after aborting configuration, data is assumed to be unaligned to word boundaries and the fpga requires a new synchronization word prior to accepting any new packets. boundary-scan configuration mode in the boundary-scan mode, no nondedicated pins are required, configuration being done entirely through the ieee 1149.1 test access port (tap). configuration through the tap uses the special cfg_in instruction. this instruction allows data input on tdi to be converted into data packets for the internal configuration bus. the following steps are required to configure the fpga through the boundary-scan port. 1. load the cfg_in instruction into the boundary-scan instruction register (ir) 2. enter the shift-dr (sdr) state 3. shift a standard configuration bitstream into tdi 4. return to run-test-idle (rti) 5. load the jstart instruction into ir 6. enter the sdr state 7. clock tck (if selected) through the startup sequence (the length is programmable) 8. return to rti configuration and readback via the tap is always available. the boundary-scan mode simply locks out the other modes. the boundary-scan mode is selected by a <10x> on the mode pins (m0, m1, m2). note that the program pin must be pulled high prior to reconfiguration. a low on the pro- gram pin resets the tap controller and no boundary scan operations can be performed. see xilinx application note xapp188 for more information on boundary-scan configu- ration. readback the configuration data stored in the spartan-iie configura- tion memory can be read back for verification. along with the configuration data it is possible to read back the con- tents of all flip-flops/latches, lut rams, and block rams. this capability is used for real-time debugging. for more detailed information see xilinx application note xapp176 , spartan-ii fpga series configuration and readback. figure 19: loading configuration data for the slave parallel mode yes no fpga driving busy high? after init goes high load one configuration byte on next cclk rising edge to crc check ds001_19_032300 no end of configuration data file? yes user drives write and cs low user drives write and cs high
spartan-iie 1.8v fpga family: functional description 20 www.xilinx.com ds077-2 (v2.1) july 9, 2003 1-800-255-7778 product specification r revision history the spartan-iie family data sheet ds077-1 , spartan-iie 1.8v fpga family: introduction and ordering information (module 1) ds077-2 , spartan-iie 1.8v fpga family: functional description (module 2) ds077-3 , spartan-iie 1.8v fpga family: dc and switching characteristics (module 3) ds077-4 , spartan-iie 1.8v fpga family: pinout tables (module 4) version no. date description 1.0 11/15/01 initial xilinx release. 2.0 11/18/02 added xc2s400e and xc2s600e. removed preliminary designation. clarified details of i/o standards, boundary scan, and configuration. 2.1 07/09/03 added hot swap description (see hot swap, hot insertion, hot socketing support ). added ta bl e 7 containing jtag idcode values. clarified configuration prom support.
ds077-3 (v2.1) july 9, 2003 www.xilinx.com 1 product specification 1-800-255-7778 ? 2003 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. definition of terms in this document, some specifications may be designated as advance or preliminary. these designations are based on the more detailed timing information used by the development system and reported in the output files. these terms are defined as follows: advance: initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. values are subject to change. use as estimates, not for production. preliminary: based on characterization. further changes are not expected. except for pin-to-pin input and output parameters, the ac parameter delay specifications included in this document are derived from measuring internal test patterns. all specifications are representative of worst-case supply voltage and junction temperature conditions. the parameters included are common to popular designs and typical applications. all specifications are subject to change without notice. dc specifications absolute maximum ratings (1) 022 spartan-iie 1.8v fpga family: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 0 0 product specification symbol description min max units v ccint supply voltage relative to gnd ?0.5 2.0 v v cco supply voltage relative to gnd ?0.5 4.0 v v ref input reference voltage ?0.5 4.0 v v in input voltage relative to gnd (2,3) ?0.5 4.0 v v ts voltage applied to 3-state output (3) ?0.5 4.0 v t stg storage temperature (ambient) ?65 +150 c t j junction temperature - +125 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. 2. v in should not exceed v cco by more than 3.6v over extended periods of time (e.g., longer than a day). 3. maximum dc overshoot must be limited to either v cco + 0.5v or 10 ma, and undershoot must be limited to ?0.5v or 10 ma, whichever is easier to achieve. the maximum ac conditions are as follows: the device pins may undershoot to ?2.0v or overshoot to v cco + 2.0v, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 ma. 4. for soldering guidelines, see the packaging information on the xilinx website. r
spartan-iie 1.8v fpga family: dc and switching characteristics 2 www.xilinx.com ds077-3 (v2.1) july 9, 2003 1-800-255-7778 product specification r recommended operating conditions dc characteristics over operating conditions symbol description min max units t j junction temperature commercial 0 85 c industrial ?40 100 c v ccint supply voltage relative to gnd (1) commercial 1.8 ? 5% 1.8 + 5% v industrial 1.8 ? 5% 1.8 + 5% v v cco supply voltage relative to gnd (2) commercial 1.2 3.6 v industrial 1.2 3.6 v t in input signal transition time (3) - 250 ns notes: 1. functional operation is guaranteed down to a minimum v ccint of 1.62v (nominal v ccint ?10%). for every 50 mv reduction in v ccint below 1.71v (nominal v ccint ?5%), all delay parameters increase by approximately 3%. 2. minimum and maximum values for v cco vary according to the i/o standard selected. 3. input and output measurement threshold is ~50% of v cco . symbol description min typ max units v drint data retention v ccint voltage (below which configuration data may be lost) 1.5 - - v v drio data retention v cco voltage (below which configuration data may be lost) 1.2 - - v i ccintq quiescent v ccint supply current (1) xc2s50e commercial - 10 200 ma industrial - 10 200 ma xc2s100e commercial - 10 200 ma industrial - 10 200 ma xc2s150e commercial - 10 300 ma industrial - 10 300 ma XC2S200E commercial - 10 300 ma industrial - 10 300 ma xc2s300e commercial - 12 300 ma industrial - 12 300 ma xc2s400e commercial - 15 300 ma industrial - 15 300 ma xc2s600e commercial - 15 400 ma industrial - 15 400 ma i ccoq quiescent v cco supply current (1) - - 2 ma i ref v ref current per v ref pin - - 20 a i l input or output leakage current per pin ?10 - +10 a c in input capacitance (sample tested) tq, pq, fg, ft packages - - 8 pf i rpu pad pull-up (when selected) @ v in = 0v, v cco = 3.3v (sample tested) (2) - - 0.25 ma i rpd pad pull-down (when selected) @ v in = 3.6v (sample tested) (2) - - 0.25 ma notes: 1. with no output current loads, no active input pull-up resistors, all i/o pins 3-stated and floating. 2. internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. these pull-up and pull-down resistors do not provide valid logic levels when input pins are connected to other circuits.
spartan-iie 1.8v fpga family: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 www.xilinx.com 3 product specification 1-800-255-7778 r power-on requirements spartan?-iie fpgas require that a minimum supply cur- rent i ccpo be provided to the v ccint lines for a successful power-on. if more current is available, the fpga can con- sume more than i ccpo min., though this cannot adversely affect reliability. a maximum limit for i ccpo is not specified. be careful when using foldback/crowbar supplies and fuses. it is possible to control the magnitude of i ccpo by limiting the supply current available to the fpga. a current limit below the trip level will avoid inadvertently activating over-current protection cir- cuits. dc input and output levels values for v il and v ih are recommended input voltages. values for v ol and v oh are guaranteed output voltages over the recommended operating conditions. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at minimum v cco with the respective i ol and i oh currents shown. other standards are sample tested. symbol description min (1) typ max units i ccpo to t a l v ccint supply current required during power-on commercial xc2s50e - xc2s300e after pcn (2) 300 - - ma before pcn (2) 500 - - ma xc2s400e - xc2s600e 500 - - ma industrial xc2s50e - xc2s300e after pcn (2) 500 - - ma before pcn (2) 2 - - a xc2s400e - xc2s600e 700 - - ma t ccpo v ccint (3,4) ramp time after pcn (2) 500 - - s before pcn (2) 2 - 50 ms i hspo ac current per pin during power-on in hot-swap applications when v in >v cco + 0.4v; duration < 10ns after pcn (2) - 60 - a notes: 1. the i ccpo requirement applies for a brief time (commonly only a few milliseconds) when v ccint ramps from 0 to 1.8v. 2. devices built after the product change notice pcn 2002-05 (see http://www.xilinx.com/bvdocs/notifications/pcn2002-05.pdf ) have improved power-on requirements. devices after the pcn have a ?t? preceding the date code as referenced in the pcn. note that the xc2s150e, xc2s400e, and xc2s600e always have this mark. devices before the pcn have an ?s? preceding the date code. note that devices before the pcn are measured with v ccint and v cco powering up simultaneously. 3. the ramp time is measured from gnd to 1.8v on a fully loaded board. 4. v ccint must not dip in the negative direction during power on. 5. i/os are not guaranteed to be disabled until v ccint is applied. 6. for more information on designing to meet the power-on specifications, refer to the application note xapp450 "power-on current requirements for the spartan-ii and spartan-iie families" . input/output standard v il v ih v ol v oh i ol i oh v, m i n v, m a x v, m i n v, m a x v, m a x v, m i n ma ma lvttl (1) ?0.5 0.8 2.0 3.6 0.4 2.4 24 ?24 lvcm os 2 ?0.5 0.7 1.7 2.7 0.4 1.9 12 ?12 lvcm os 18 ?0.5 35% v cco 65% v cco 1.95 0.4 v cco ? 0.4 8 ?8 pci, 3.3v ?0.5 30% v cco 50% v cco v cco + 0.5 10% v cco 90% v cco note (2) note (2) gtl ?0.5 v ref ? 0.05 v ref + 0.05 3.6 0.4 - 40 - gtl+ ?0.5 v ref ? 0.1 v ref + 0.1 3.6 0.6 - 36 - hstl i ?0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 8 ?8
spartan-iie 1.8v fpga family: dc and switching characteristics 4 www.xilinx.com ds077-3 (v2.1) july 9, 2003 1-800-255-7778 product specification r lvds dc specifications lvpecl dc specifications these values are valid at the output of the source termina- tion pack shown under lvpecl, with a 100 ? differential load only. the v oh levels are 200 mv below standard lvpecl levels and are compatible with devices tolerant of lower common-mode ranges. the following table summa- rizes the dc output specifications of lvpecl. hstl iii ?0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 24 ?8 hstl iv ?0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 48 ?8 sstl3 i ?0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.6 v ref + 0.6 8 ?8 sstl3 ii ?0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.8 v ref + 0.8 16 ?16 sstl2 i ?0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.61 v ref + 0.61 7.6 ?7.6 sstl2 ii ?0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.8 v ref + 0.8 15.2 ?15.2 ctt ?0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.4 v ref + 0.4 8 ?8 agp ?0.5 v ref ? 0.2 v ref + 0.2 3.6 10% v cco 90% v cco note (2) note (2) notes: 1. v ol and v oh for lower drive currents are sample tested. 2. tested according to the relevant specifications. symbol description conditions min typ max units v cco supply voltage 2.375 2.5 2.625 v v oh output high voltage for q and q r t = 100 ? across q and q signals 1.25 1.425 1.6 v v ol output low voltage for q and q r t = 100 ? across q and q signals 0.9 1.075 1.25 v v odiff differential output voltage (q ? q ), q = high or (q ? q), q = high r t = 100 ? across q and q signals 250 350 450 mv v ocm output common-mode voltage r t = 100 ? across q and q signals 1.125 1.25 1.375 v v idiff differential input voltage (q ? q ), q = high or (q ? q), q = high common-mode input voltage = 1.25 v 100 350 - mv v icm input common-mode voltage differential input voltage = 350 mv 0.2 1.25 2.2 v input/output standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma dc parameter min max min max min max units v cco 3.0 3.3 3.6 v v oh 1.8 2.11 1.92 2.28 2.13 2.41 v v ol 0.96 1.27 1.06 1.43 1.30 1.57 v v ih 1.49 2.72 1.49 2.72 1.49 2.72 v v il 0.86 2.125 0.86 2.125 0.86 2.125 v differential input voltage 0.3 - 0.3 - 0.3 - v
spartan-iie 1.8v fpga family: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 www.xilinx.com 5 product specification 1-800-255-7778 r switching characteristics internal timing parameters are derived from measuring internal test patterns. listed below are representative val- ues. for more specific, more precise, and worst-case guar- anteed data, use the values reported by the static timing analyzer (trace in the xilinx development system) and back-annotated to the simulation netlist. all timing parame- ters assume worst-case operating conditions (supply volt- age and junction temperature). values apply to all spartan-iie devices unless otherwise noted. global clock input to output delay for lvttl, with dll (pin-to-pin) (1) global clock input to output delay for lvttl, without dll (pin-to-pin) (1) symbol description speed grade units all -7 -6 min max max t ickofdll lvttl global clock input to output delay using output flip-flop for lvttl, 12 ma, fast slew rate, with dll. 1.0 3.1 3.1 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 50% v cc threshold with 35 pf external capacitive load for lvttl. the 35 pf load does not apply to the min values. for other i/o standards and different loads, see the tables constants for calculating tioop and delay measurement methodology , page 11 . 3. dll output jitter is already included in the timing calculation. 4. for data output with different standards, adjust delays with the values shown in iob output delay adjustments for different standards(1) , page 10 . for a global clock input with standards other than lvttl, adjust delays with values from the i/o standard global clock input adjustments , page 12 . symbol description device speed grade units all -7 -6 min max max t ickof lvttl global clock input to output delay using output flip-flop for lvttl, 12 ma, fast slew rate, without dll. xc2s50e 1.5 4.4 4.6 ns xc2s100e 1.5 4.4 4.6 ns xc2s150e 1.5 4.5 4.7 ns XC2S200E 1.5 4.5 4.7 ns xc2s300e 1.5 4.5 4.7 ns xc2s400e 1.5 4.6 4.8 ns xc2s600e 1.6 4.7 4.9 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 50% v cc threshold with 35 pf external capacitive load for lvttl. the 35 pf load does not apply to the min values. for other i/o standards and different loads, see the tables constants for calculating tioop and delay measurement methodology , page 11 . 3. for data output with different standards, adjust delays with the values shown in iob output delay adjustments for different standards(1) , page 10 . for a global clock input with standards other than lvttl, adjust delays with values from the i/o standard global clock input adjustments , page 12 .
spartan-iie 1.8v fpga family: dc and switching characteristics 6 www.xilinx.com ds077-3 (v2.1) july 9, 2003 1-800-255-7778 product specification r global clock setup and hold for lvttl standard, with dll (pin-to-pin) global clock setup and hold for lvttl standard, without dll (pin-to-pin) symbol description speed grade units -7 -6 min min t psdll / t phdll input setup and hold time relative to global clock input signal for lvttl standard, no delay, iff, (1) with dll 1.6 / 0 1.7 / 0 ns notes: 1. iff = input flip-flop or latch 2. setup time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load. 3. dll output jitter is already included in the timing calculation. 4. for data input with different standards, adjust the setup time delay by the values shown in iob input delay adjustments for different standards , page 8 . for a global clock input with standards other than lvttl, adjust delays with values from the i/o standard global clock input adjustments , page 12 . 5. a zero hold time listing indicates no hold time or a negative hold time. symbol description device speed grade units -7 -6 min min t psfd / t phfd input setup and hold time relative to global clock input signal for lvttl standard, with delay, iff, (1) without dll xc2s50e 1.8 / 0 1.8 / 0 ns xc2s100e 1.8 / 0 1.8 / 0 ns xc2s150e 1.9 / 0 1.9 / 0 ns XC2S200E 1.9 / 0 1.9 / 0 ns xc2s300e 2.0 / 0 2.0 / 0 ns xc2s400e 2.0 / 0 2.0 / 0 ns xc2s600e 2.1 / 0 2.1 / 0 ns notes: 1. iff = input flip-flop or latch 2. setup time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load. 3. for data input with different standards, adjust the setup time delay by the values shown in iob input delay adjustments for different standards , page 8 . for a global clock input with standards other than lvttl, adjust delays with values from the i/o standard global clock input adjustments , page 12 .
spartan-iie 1.8v fpga family: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 www.xilinx.com 7 product specification 1-800-255-7778 r iob input switchi ng characteristics (1) input delays associated with the pad are specified for lvttl levels. for other standards, adjust the delays with the values shown in iob input delay adjustments for different standards , page 8 . symbol description device speed grade units -7 -6 min max min max propagation delays t iopi pad to i output, no delay all 0.4 0.8 0.4 0.8 ns t iopid pad to i output, with delay all 0.5 1.0 0.5 1.0 ns t iopli pad to output iq via transparent latch, no delay all 0.7 1.5 0.7 1.6 ns t ioplid pad to output iq via transparent latch, with delay xc2s50e 1.3 3.0 1.3 3.1 ns xc2s100e 1.3 3.0 1.3 3.1 ns xc2s150e 1.3 3.2 1.3 3.3 ns XC2S200E 1.3 3.2 1.3 3.3 ns xc2s300e 1.3 3.2 1.3 3.3 ns xc2s400e 1.4 3.2 1.4 3.4 ns xc2s600e 1.5 3.5 1.5 3.7 ns sequential delays t iockiq clock clk to output iq all 0.1 0.7 0.1 0.7 ns setup/hold times with respect to clock clk t iopick / t ioickp pad, no delay all 1.4 / 0 - 1.5 / 0 - ns t iopickd / t ioickpd pad, with delay xc2s50e 2.9 / 0 - 2.9 / 0 - ns xc2s100e 2.9 / 0 - 2.9 / 0 - ns xc2s150e 3.1 / 0 - 3.1 / 0 - ns XC2S200E 3.1 / 0 - 3.1 / 0 - ns xc2s300e 3.1 / 0 - 3.1 / 0 - ns xc2s400e 3.2 / 0 - 3.2 / 0 - ns xc2s600e 3.5 / 0 - 3.5 / 0 - ns t ioiceck / t iockice ice input all 0.7 / 0.01 - 0.7 / 0.01 - ns set/reset delays t iosrcki sr input (iff, synchronous) all 0.9 - 1.0 - ns t iosriq sr input to iq (asynchronous) all 0.5 1.2 0.5 1.4 ns t gsrq gsr to output iq all 3.8 8.5 3.8 9.7 ns notes: 1. input timing for lvttl is measured at 1.4v. for other i/o standards, see the table delay measurement methodology , page 11 .
spartan-iie 1.8v fpga family: dc and switching characteristics 8 www.xilinx.com ds077-3 (v2.1) july 9, 2003 1-800-255-7778 product specification r iob input delay adjustments for different standards input delays associated with the pad are specified for lvttl. for other standards, adjust the delays by the values shown. a delay adjusted in this way constitutes a worst-case limit. symbol description standard speed grade units -7 -6 data input delay adjustments t ilvttl standard-specific data input delay adjustments lvttl 0 0 ns t ilvcmos2 lv c m o s 2 0 0 ns t ilvcmos18 lv c m o s 1 8 0.20 0.20 ns t ilvds lv d s 0.15 0.15 ns t ilvpecl lv p e c l 0.15 0.15 ns t ipci33_3 pci, 33 mhz, 3.3v 0.08 0.08 ns t ipci66_3 pci, 66 mhz, 3.3v ?0.11 ?0.11 ns t igtl gtl 0.14 0.14 ns t igtlp gtl+ 0.14 0.14 ns t ihstl hstl 0.04 0.04 ns t isstl2 sstl2 0.04 0.04 ns t isstl3 sstl3 0.04 0.04 ns t ictt ctt 0.10 0.10 ns t iagp agp 0.04 0.04 ns
spartan-iie 1.8v fpga family: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 www.xilinx.com 9 product specification 1-800-255-7778 r iob output switching characteristics output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays with the values shown in iob output delay adjustments for different standards(1) , page 10 . symbol description speed grade units -7 -6 min max min max propagation delays t ioop o input to pad 1.0 2.7 1.0 2.9 ns t ioolp o input to pad via transparent latch 1.2 3.1 1.2 3.4 ns 3-state delays t iothz t input to pad high impedance (1) 0.7 1.7 0.7 1.9 ns t ioton t input to valid data on pad 1.1 2.9 1.1 3.1 ns t iotlphz t input to pad high impedance via transparent latch (1) 0.8 2.0 0.8 2.2 ns t iotlpon t input to valid data on pad via transparent latch 1.2 3.2 1.2 3.4 ns t gts gts to pad high impedance (1) 1.9 4.6 1.9 4.9 ns sequential delays t iockp clock clk to pad 0.9 2.8 0.9 2.9 ns t iockhz clock clk to pad high impedance (synchronous) (1) 0.7 2.0 0.7 2.2 ns t iockon clock clk to valid data on pad (synchronous) 1.1 3.2 1.1 3.4 ns setup/hold times with respect to clock clk t ioock / t iocko o input 1.0 / 0 - 1.1 / 0 - ns t iooceck / t iockoce oce input 0.7 / 0 - 0.7 / 0 - ns t iosrcko / t iockosr sr input (off) 0.9 / 0 - 1.0 / 0 - ns t iotck / t iockt 3-state setup times, t input 0.6 / 0 - 0.7 / 0 - ns t iotceck / t iocktce 3-state setup times, tce input 0.6 / 0 - 0.8 / 0 - ns t iosrckt / t iocktsr 3-state setup times, sr input (tff) 0.9 / 0 - 1.0 / 0 - ns set/reset delays t iosrp sr input to pad (asynchronous) 1.2 3.3 1.2 3.5 ns t iosrhz sr input to pad high impedance (asynchronous) (1) 1.0 2.4 1.0 2.7 ns t iosron sr input to valid data on pad (asynchronous) 1.4 3.7 1.4 3.9 ns t iogsrq gsr to pad 3.8 8.5 3.8 9.7 ns notes: 1. three-state turn-off delays should not be adjusted.
spartan-iie 1.8v fpga family: dc and switching characteristics 10 www.xilinx.com ds077-3 (v2.1) july 9, 2003 1-800-255-7778 product specification r iob output delay adjustments for different standards(1) output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays by the values shown. a delay adjusted in this way constitutes a worst-case limit. symbol description standard speed grade units -7 -6 output delay adjustments (adj) t olvttl_s2 standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, c sl ) lvttl, slow, 2 ma 14.7 14.7 ns t olvttl_s4 4 ma 7.5 7.5 ns t olvttl_s6 6 ma 4.8 4.8 ns t olvttl_s8 8 ma 3.0 3.0 ns t olvttl_s12 12 ma 1.9 1.9 ns t olvttl_s16 16 ma 1.7 1.7 ns t olvttl_s24 24 ma 1.3 1.3 ns t olvttl_f2 lvttl, fast, 2 ma 13.1 13.1 ns t olvttl_f4 4 ma 5.3 5.3 ns t olvttl_f6 6 ma 3.1 3.1 ns t olvttl_f8 8 ma 1.0 1.0 ns t olvttl_f12 12 ma 0 0 ns t olvttl_f16 16 ma ?0.05 ?0.05 ns t olvttl_f24 24 ma ?0.20 ?0.20 ns t olvcmos2 lv c m o s 2 0.09 0.09 ns t olvcmos18 lv c m o s 1 8 0.7 0.7 ns t olvds lv d s ?1.2 ?1.2 ns t olvpecl lv p e c l ?0.41 ?0.41 ns t opci33_3 pci, 33 mhz, 3.3v 2.3 2.3 ns t opci66_3 pci, 66 mhz, 3.3v ?0.41 ?0.41 ns t ogtl gtl 0.49 0.49 ns t ogtlp gtl+ 0.8 0.8 ns t ohstl_i hstl i ?0.51 ?0.51 ns t ohstl_iii hstl iii ?0.91 ?0.91 ns t ohstl_iv hstl iv ?1.01 ?1.01 ns t osstl2_i sstl2 i ?0.51 ?0.51 ns t osslt2_ii sstl2 ii ?0.91 ?0.91 ns t osstl3_i sstl3 i ?0.51 ?0.51 ns t osstl3_ii sstl3 ii ?1.01 ?1.01 ns t octt ctt ?0.61 ?0.61 ns t oagp agp ?0.91 ?0.91 ns notes: 1. output timing is measured at 1.4v with 35 pf external capacitive load for lvttl. for other i/o standards and different loads, see the tables constants for calculating tioop and delay measurement methodology , page 11 .
spartan-iie 1.8v fpga family: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 www.xilinx.com 11 product specification 1-800-255-7778 r calculation of t ioop as a function of capacitance t ioop is the propagation delay from the o input of the iob to the pad. the values for t ioop are based on the standard capacitive load (c sl ) for each i/o standard as listed in the table constants for calculating tioop , below. for other capacitive loads, use the formulas below to calcu- late an adjusted propagation delay, t ioop1 . t ioop1 = t ioop + adj + (c load ? c sl ) * f l where: adj is selected from iob output delay adjustments for different standards(1) , page 10 , according to the i/o standard used c load is the capacitive load for the design f l is the capacitance scaling factor delay measurement methodology standard v l (1) v h (1) meas. point v ref typ (2) lvttl 0 3 1.4 - lv c m o s 2 0 2.5 1.125 - pci33_3 per pci spec - pci66_3 per pci spec - gtl v ref ? 0.2 v ref + 0.2 v ref 0.80 gtl+ v ref ? 0.2 v ref + 0.2 v ref 1.0 hstl class i v ref ? 0.5 v ref + 0.5 v ref 0.75 hstl class iii v ref ? 0.5 v ref + 0.5 v ref 0.90 hstl class iv v ref ? 0.5 v ref + 0.5 v ref 0.90 sstl3 i and ii v ref ? 1.0 v ref + 1.0 v ref 1.5 sstl2 i and ii v ref ? 0.75 v ref + 0.75 v ref 1.25 ctt v ref ? 0.2 v ref + 0.2 v ref 1.5 agp v ref ? (0.2xv cco ) v ref + (0.2xv cco ) v ref per agp spec lv d s 1.2 ? 0.125 1.2 + 0.125 1.2 lvpecl 1.6 ? 0.3 1.6 + 0.3 1.6 notes: 1. input waveform switches between v l and v h . 2. measurements are made at v ref typ, maximum, and minimum. worst-case values are reported. 3. i/o parameter measurements are made with the capacitance values shown in the following table, constants for calculating tioop . refer to application note xapp179 for appropriate terminations. 4. i/o standard measurements are reflected in the ibis model information except where the ibis format precludes it. constants for calculating t ioop standard c sl (1) (pf) f l (ns/pf) lvttl fast slew rate, 2 ma drive 35 0.41 lvttl fast slew rate, 4 ma drive 35 0.20 lvttl fast slew rate, 6 ma drive 35 0.13 lvttl fast slew rate, 8 ma drive 35 0.079 lvttl fast slew rate, 12 ma drive 35 0.044 lvttl fast slew rate, 16 ma drive 35 0.043 lvttl fast slew rate, 24 ma drive 35 0.033 lvttl slow slew rate, 2 ma drive 35 0.41 lvttl slow slew rate, 4 ma drive 35 0.20 lvttl slow slew rate, 6 ma drive 35 0.100 lvttl slow slew rate, 8 ma drive 35 0.086 lvttl slow slew rate, 12 ma drive 35 0.058 lvttl slow slew rate, 16 ma drive 35 0.050 lvttl slow slew rate, 24 ma drive 35 0.048 lv c m o s 2 35 0.041 lv c m o s 1 8 35 0.050 pci 33 mhz 3.3v 10 0.050 pci 66 mhz 3.3v 10 0.033 gtl 0 0.014 gtl+ 0 0.017 hstl class i 20 0.022 hstl class iii 20 0.016 hstl class iv 20 0.014 sstl2 class i 30 0.028 sstl2 class ii 30 0.016 sstl3 class i 30 0.029 sstl3 class ii 30 0.016 ctt 20 0.035 agp 10 0.037 notes: 1. i/o parameter measurements are made with the capacitance values shown above. refer to application note xapp179 for appropriate terminations. 2. i/o standard measurements are reflected in the ibis model information except where the ibis format precludes it.
spartan-iie 1.8v fpga family: dc and switching characteristics 12 www.xilinx.com ds077-3 (v2.1) july 9, 2003 1-800-255-7778 product specification r clock distribution swit ching characteristics t gpio is specified for lvttl levels. for other standards, adjust t gpio with the values shown in i/o standard global clock input adjustments . i/o standard global clock input adjustments delays associated with a global clock input pad are specified for lvttl levels. for other standards, adjust the delays by the values shown. a delay adjusted in this way constitutes a worst-case limit. symbol description speed grade units -7 -6 max max gclk iob and buffer t gpio global clock pad to output 0.7 0.7 ns t gio global clock buffer i input to o output 0.45 0.5 ns symbol description standard speed grade units -7 -6 data input delay adjustments t gplvttl standard-specific global clock input delay adjustments lvttl 0 0 ns t gplvcmos2 lvcm os 2 0 0 ns t gplvcmos18 lv c m o s 1 8 0.2 0.2 ns t gplvcds lv d s 0.38 0.38 ns t gplvpecl lvcpecl 0.38 0.38 ns t gppci33_3 pci, 33 mhz, 3.3v 0.08 0.08 ns t gppci66_3 pci, 66 mhz, 3.3v ?0.11 ?0.11 ns t gpgtl gtl 0.37 0.37 ns t gpgtlp gtl+ 0.37 0.37 ns t gphstl hstl 0.27 0.27 ns t gpsstl2 sstl2 0.27 0.27 ns t gpsstl3 sstl3 0.27 0.27 ns t gpctt ctt 0.33 0.33 ns t gpagp agp 0.27 0.27 ns notes: 1. input timing for gplvttl is measured at 1.4v. for other i/o standards, see the table delay measurement methodology , page 11 .
spartan-iie 1.8v fpga family: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 www.xilinx.com 13 product specification 1-800-255-7778 r dll timing parameters because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. the following guidelines reflect worst-case values across the recommended operating con- ditions. dll clock tolerance, jitte r, and phase information all dll output jitter and phase specifications were deter- mined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. figure 1, page 14 , provides definitions for various parame- ters in the table below. symbol description f clkin speed grade units -7 -6 min max min max f clkinhf input clock frequency (clkdllhf) - 60 320 60 275 mhz f clkinlf input clock frequency (clkdll) - 25 160 25 135 mhz t dllpw input clock pulse width 25 mhz 5.0 - 5.0 - ns 50 mhz 3.0 - 3.0 - ns 100 mhz 2.4 - 2.4 - ns 150 mhz 2.0 - 2.0 - ns 200 mhz 1.8 - 1.8 - ns 250 mhz 1.5 - 1.5 - ns 300 mhz 1.3 - na - symbol description f clkin clkdllhf clkdll units min max min max t iptol input clock period tolerance - 1.0 - 1.0 ns t ijitcc input clock jitter tolerance (cycle-to-cycle) - 150 - 300 ps t lock time required for dll to acquire lock (1) > 60 mhz - 20 - 20 s 50-60 mhz - - - 25 s 40-50 mhz - - - 50 s 30-40 mhz - - - 90 s 25-30 mhz - - - 120 s t ojitcc output jitter (cycle-to-cycle) for any dll clock output (2) - 60 - 60 ps t phio phase offset between clkin and clko (3) - 100 - 100 ps t phoo phase offset between clock outputs on the dll (4) - 140 - 140 ps t phiom phase difference between clkin and clko (5) - 160 - 160 ps t phoom phase difference between clock outputs on the dll (6) - 200 - 200 ps notes: 1. commercial operating conditions. add 30% for industrial operating conditions. 2. output jitter is cycle-to-cycle jitter measured on the dll output clock, excluding input clock jitter. 3. phase offset between clkin and clko is the worst-case fixed time difference between rising edges of clkin and clko, excluding output jitter and input clock jitter. 4. phase offset between clock outputs on the dll is the worst-case fixed time difference between rising edges of any two dll outputs, excluding output jitter and input clock jitter. 5. maximum phase difference between clkin and clko is the sum of output jitter and phase offset between clkin and clko, or the greatest difference between clkin and clko rising edges due to dll alone ( excluding input clock jitter). 6. maximum phase difference between clock outputs on the dll is the sum of output jitter and phase offset between any dll clock outputs, or the greatest difference between any two dll output rising edges due to dll alone ( excluding input clock jitter).
spartan-iie 1.8v fpga family: dc and switching characteristics 14 www.xilinx.com ds077-3 (v2.1) july 9, 2003 1-800-255-7778 product specification r figure 1: period tolerance and clock jitter period tolerance: the allowed input clock period change in nanoseconds. output jitter: the difference between an ideal reference clock edge and the actual design. t clkin + t iptol _ ds001_52_090800 actual period + jitter +/- jitter + maximum phase difference phase offset and maximum phase difference + phase offset ideal period 1 f clkin t = clkin
spartan-iie 1.8v fpga family: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 www.xilinx.com 15 product specification 1-800-255-7778 r clb switching characteristics delays originating at f/g inputs vary slightly according to the input used. the values listed below are worst-case. precise values are provided by the timing analyzer. symbol description speed grade units -7 -6 min max min max combinatorial delays t ilo 4-input function: f/g inputs to x/y outputs 0.18 0.42 0.18 0.47 ns t if5 5-input function: f/g inputs to f5 output 0.3 0.8 0.3 0.9 ns t if5x 5-input function: f/g inputs to x output 0.3 0.8 0.3 0.9 ns t if6y 6-input function: f/g inputs to y output via f6 mux 0.3 0.9 0.3 1.0 ns t f5iny 6-input function: f5in input to y output 0.04 0.2 0.04 0.22 ns t ifnctl incremental delay routing through transparent latch to xq/yq outputs - 0.7 - 0.8 ns t byyb by input to yb output 0.18 0.46 0.18 0.51 ns sequential delays t cko ff clock clk to xq/yq outputs 0.3 0.9 0.3 1.0 ns t cklo latch clock clk to xq/yq outputs 0.3 0.9 0.3 1.0 ns setup/hold times with respect to clock clk t ick / t cki 4-input function: f/g inputs 1.0 / 0 - 1.1 / 0 - ns t if5ck / t ckif5 5-input function: f/g inputs 1.4 / 0 - 1.5 / 0 - ns t f5inck / t ckf5in 6-input function: f5in input 0.8 / 0 - 0.8 / 0 - ns t if6ck / t ckif6 6-input function: f/g inputs via f6 mux 1.5 / 0 - 1.6 / 0 - ns t dick / t ckdi bx/by inputs 0.7 / 0 - 0.8 / 0 - ns t ceck / t ckce ce input 0.7 / 0 - 0.7 / 0 - ns t rck / t ckr sr/by inputs (synchronous) 0.52 / 0 - 0.6 / 0 - ns clock clk t ch pulse width, high 1.3 - 1.4 - ns t cl pulse width, low 1.3 - 1.4 - ns set/reset t rpw pulse width, sr/by inputs 2.1 - 2.4 - ns t rq delay from sr/by inputs to xq/yq outputs (asynchronous) 0.3 0.9 0.3 1.0 ns f tog toggle frequency (for export control) - 400 - 357 mhz
spartan-iie 1.8v fpga family: dc and switching characteristics 16 www.xilinx.com ds077-3 (v2.1) july 9, 2003 1-800-255-7778 product specification r clb arithmetic switching characteristics setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. precise values are provided by the timing analyzer. symbol description speed grade units -7 -6 min max min max combinatorial delays t opx f operand inputs to x via xor - 0.8 - 0.8 ns t opxb f operand input to xb output - 0.8 - 0.9 ns t opy f operand input to y via xor - 1.4 - 1.5 ns t opyb f operand input to yb output - 1.1 - 1.3 ns t opcyf f operand input to cout output - 0.9 - 1.0 ns t opgy g operand inputs to y via xor - 0.8 - 0.9 ns t opgyb g operand input to yb output - 1.2 - 1.3 ns t opcyg g operand input to cout output - 0.9 - 1.0 ns t bxcy bx initialization input to cout - 0.51 - 0.6 ns t cinx cin input to x output via xor - 0.6 - 0.7 ns t cinxb cin input to xb - 0.07 - 0.1 ns t ciny cin input to y via xor - 0.7 - 0.7 ns t cinyb cin input to yb - 0.4 - 0.5 ns t byp cin input to cout output - 0.14 - 0.15 ns multiplier operation t fandxb f1/2 operand inputs to xb output via and - 0.35 - 0.4 ns t fandyb f1/2 operand inputs to yb output via and - 0.7 - 0.8 ns t fandcy f1/2 operand inputs to cout output via and - 0.5 - 0.6 ns t gandyb g1/2 operand inputs to yb output via and - 0.6 - 0.7 ns t gandcy g1/2 operand inputs to cout output via and - 0.3 - 0.4 ns setup/hold times with respect to clock clk t cckx / t ckcx cin input to ffx 1.2 / 0 - 1.3 / 0 - ns t ccky / t ckcy cin input to ffy 1.2 / 0 - 1.3 / 0 - ns
spartan-iie 1.8v fpga family: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 www.xilinx.com 17 product specification 1-800-255-7778 r clb distributed ram switching characteristics clb shift register switching characteristics block ram switching characteristics symbol description speed grade units -7 -6 min max min max sequential delays t shcko16 clock clk to x/y outputs (we active, 16 x 1 mode) 0.6 1.5 0.6 1.7 ns t shcko32 clock clk to x/y outputs (we active, 32 x 1 mode) 0.8 1.9 0.8 2.1 ns setup/hold times with respect to clock clk t as / t ah f/g address inputs 0.42 / 0 - 0.5 / 0 - ns t ds / t dh bx/by data inputs (din) 0.53 / 0 - 0.6 / 0 - ns t ws / t wh ce input (ws) 0.7 / 0 - 0.8 / 0 - ns clock clk t wph pulse width, high 2.1 - 2.4 - ns t wpl pulse width, low 2.1 - 2.4 - ns t wc clock period to meet address write cycle time 4.2 - 4.8 - ns symbol description speed grade units -7 -6 min max min max sequential delays t reg clock clk to x/y outputs 1.2 2.9 1.2 3.2 ns setup/hold times with respect to clock clk t shdick bx/by data inputs (din) 0.53 / 0 - 0.6 / 0 - ns t shceck ce input (ws) 0.7 / 0 - 0.8 / 0 - ns clock clk t srph pulse width, high 2.1 - 2.4 - ns t srpl pulse width, low 2.1 - 2.4 - ns symbol description speed grade units -7 -6 min max min max sequential delays t bcko clock clk to dout output 0.6 3.1 0.6 3.5 ns setup/hold times with respect to clock clk t back / t bcka addr inputs 1.0 / 0 - 1.1 / 0 - ns t bdck / t bckd din inputs 1.0 / 0 - 1.1 / 0 - ns t beck / t bcke en inputs 2.2 / 0 - 2.5 / 0 - ns t brck / t bckr rst input 2.1 / 0 - 2.3 / 0 - ns t bwck / t bckw wen input 2.0 / 0 - 2.2 / 0 - ns clock clk t bpwh pulse width, high 1.4 - 1.5 - ns t bpwl pulse width, low 1.4 - 1.5 - ns t bccs clka -> clkb setup time for different ports 2.7 - 3.0 - ns
spartan-iie 1.8v fpga family: dc and switching characteristics 18 www.xilinx.com ds077-3 (v2.1) july 9, 2003 1-800-255-7778 product specification r tbuf switching characteristics jtag test access port switching characteristics configuration switching characteristics symbol description speed grade units -7 -6 max max t io in input to out output 0 0 ns t off tri input to out output high impedance 0.1 0.11 ns t on tri input to valid data on out output 0.1 0.11 ns symbol description speed grade units -7 -6 min max min max setup/hold times with respect to tck t ta p t c k / t tcktap tms and tdi setup times and hold times 4.0 / 2.0 - 4.0 / 2.0 - ns sequential delays t tcktdo output delay from clock tck to output tdo - 11.0 - 11.0 ns f tck tck clock frequency - 33 - 33 mhz notes: 1. before configuration can begin, v ccint and v cco bank 2 must reach the recommended operating voltage. figure 2: configuration timing on power-up ds001_12_102301 t por t pl t icck valid cclk output or input m0, m1, m2 (required) program init v cc (1) . symbol description all devices units min max t por power-on reset - 2 ms t pl program latency - 100 s t icck cclk output delay (master serial mode only) 0.5 4 s t program program pulse width 300 - ns
spartan-iie 1.8v fpga family: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 www.xilinx.com 19 product specification 1-800-255-7778 r figure 3: slave serial mode timing figure 4: master serial mode timing t cch t cco t ccl t ccd t dcc din cclk dout (output) ds001_16_032300 . symbol description all devices units min max t dcc / t ccd cclk din setup/hold 5 / 0 - ns t cco dout - 12 ns t cch high time 5 - ns t ccl low time 5 - ns f cc maximum frequency - 66 mhz serial data in cclk (output) serial dout (output) t dsck t cco t ckds ds001_17_110101 . symbol description all devices units min max t dsck / t ckds cclk din setup/hold 5 / 0 - ns t cco dout - 12 ns f cc frequency tolerance with respect to nominal ?30% +45% -
spartan-iie 1.8v fpga family: dc and switching characteristics 20 www.xilinx.com ds077-3 (v2.1) july 9, 2003 1-800-255-7778 product specification r figure 5: slave parallel (selectmap) mode write timing figure 6: slave parallel (selectmap) mode write abort waveforms ds001_20_061200 cclk no write write no write write data[7:0] cs write t smdcc t smccd t smckby t smcccs t smwcc t smccw t smcscc busy symbol description all devices units min max t smdcc / t smccd cclk d0-d7 setup/hold 5 / 1 - ns t smcscc / t smcccs cs setup/hold 7 / 1 - ns t smccw / t smwcc write setup/hold 7 / 1 - ns t smckby busy propagation delay - 12 ns f cc frequency - 66 mhz f ccnh frequency with no handshake - 50 mhz ds001_21_032300 cclk cs write abort data[7:0] busy
spartan-iie 1.8v fpga family: dc and switching characteristics ds077-3 (v2.1) july 9, 2003 www.xilinx.com 21 product specification 1-800-255-7778 r revision history the spartan-iie family data sheet ds077-1 , spartan-iie 1.8v fpga family: introduction and ordering information (module 1) ds077-2 , spartan-iie 1.8v fpga family: functional description (module 2) ds077-3 , spartan-iie 1.8v fpga family: dc and switching characteristics (module 3) ds077-4 , spartan-iie 1.8v fpga family: pinout tables (module 4) version no. date description 1.0 11/15/01 initial xilinx release. 1.1 06/28/02 added -7 speed grade and extended dll specs to industrial. 2.0 11/18/02 added xc2s400e and xc2s600e. added minimum specifications. added reference to xapp450 for power-on requirements. removed preliminary designation. 2.1 07/09/03 added iccintq typical values. reduced iccpo power-on current requirements. relaxed tccpo power-on ramp requirements. added ihspo to describe current in hot-swap applications. updated tpsfd / tphfd description to indicate use of delay element.
spartan-iie 1.8v fpga family: dc and switching characteristics 22 www.xilinx.com ds077-3 (v2.1) july 9, 2003 1-800-255-7778 product specification r
ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 1 ? 2003 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. 054 spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 0 0 product specification r pin definitions pad name dedicated pin direction description gck0, gck1, gck2, gck3 no input clock input pins that connect to global clock buffers or dll inputs. these pins become user inputs when not needed for clocks. dll no input clock input pins that connect to dll input or feedback clocks. differential clock input (n input of pair) when paired with adjacent gck input. becomes a user i/o when not needed for clocks. m0, m1, m2 ye s input mode pins used to specify the configuration mode. cclk ye s input or output the configuration clock i/o pin. it is an input for slave parallel and slave serial modes, and output in master serial mode. after configuration, it is an input only with don?t care logic levels. program ye s input initiates a configuration sequence when asserted low. done ye s bidirectional indicates that configuration loading is complete, and that the start-up sequence is in progress. the output may be open drain. init no bidirectional (open-drain) when low, indicates that the configuration memory is being cleared. goes high to indicate the end of initialization. goes back low to indicate a crc error. this pin becomes a user i/o after configuration. dout/busy no output in slave parallel mode, busy controls the rate at which configuration data can be loaded. it is not needed below 50 mhz. this pin becomes a user i/o after configuration unless the slave parallel port is retained. in serial modes, dout provides configuration data to downstream devices in a daisy-chain. this pin becomes a user i/o after configuration. d0/din, d1, d2, d3, d4, d5, d6, d7 no input or output in slave parallel mode, d0-d7 are configuration data input pins. during readback, d0-d7 are output pins. these pins become user i/os after configuration unless the slave parallel port is retained. in serial modes, din is the single data input. this pin becomes a user i/o after configuration. write no input in slave parallel mode, the active-low write enable signal. this pin becomes a user i/o after configuration unless the slave parallel port is retained. cs no input in slave parallel mode, the active-low chip select signal. this pin becomes a user i/o after configuration unless the slave parallel port is retained. tdi, tdo, tms, tck ye s mixed boundary scan test access port pins (ieee 1149.1). v ccint ye s input 1.8v power supply pins for the internal core logic.
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 2 1-800-255-7778 product specification r spartan-iie package pinouts the spartan-iie family of fpgas is available in five popular, low-cost packages, including plastic quad flat packs and fine-pitch ball grid arrays. package drawings can be found at http://www.xilinx.com/xlnx/xweb/xil_publications_index. jsp?category=package+drawings . family members have footprint compatibility across devices provided in the same package, with minor exceptions due to the smaller number of i/o in smaller devices or due to lvds/lvpecl pin pair- ing. the spartan-iie family is not footprint compatible with any other fpga family. the following package-specific pinout tables indicate function, pin, and bank information for all devices available in that package. the pinouts follow the pad locations around the die, starting from pin 1 on the qfp packages. low voltage differential signals (lvds and lvpecl) the spartan-iie family features low-voltage differential sig- naling (lvds and lvpecl). each signal utilizes two pins on the spartan-iie device, known as differential pin pairs. each differential pin pair has a positive (p) and a negative (n) pin. these pairs are labeled in the following manner. i/o, l#[p/n][-/_y/_yy] where l = lvds or lvpecl pin # = pin pair number p = positive n = negative _y = asynchronous output allowed (device-dependent) _yy = asynchronous output allowed (all devices) v cco ye s input power supply pins for output drivers (1.5v, 1.8v, 2.5v, or 3.3v subject to banking rules in module 2, functional description ). v ref no input input threshold reference voltage pins. become user i/os when an external threshold voltage is not needed (subject to banking rules in module 2, functional description ). gnd ye s input ground. all must be connected. i rdy, tr dy no see pci core documentation these signals can only be accessed when using xilinx pci cores. if the cores are not used, these pins are available as user i/os. l#[p/n] (e.g., l0p) no bidirectional differential i/o with synchronous output. p = positive, n = negative. the number (#) is used to associate the two pins of a differential pair. becomes a general user i/o when not needed for differential signals. l#[p/n]_y (e.g., l0p_y) no bidirectional differential i/o with asynchronous or synchronous output (asynchronous output not compatible for all densities in a package). p = positive, n = negative. the number (#) is used to associate the two pins of a differential pair. becomes a general user i/o when not needed for differential signals. l#[p/n]_yy (e.g., l0p_yy) no bidirectional differential i/o with asynchronous or synchronous output (compatible for all densities in a package). p = positive, n = negative. the number (#) is used to associate the two pins of a differential pair. becomes a general user i/o when not needed for differential signals. i/o no bidirectional these pins can be configured to be input and/or output after configuration is completed. unused i/os are disabled with a weak pull-down resistor. after power-on and before configuration is completed, these pins are either pulled up or left floating according to the mode pin values. see module 3, dc and switching characteristics for power-on characteristics. pin definitions (continued) pad name dedicated pin direction description
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 3 r synchronous or asynchronous i/o pins for differential signals can either be synchronous or asynchronous, input or output. differential signaling requires the pins of each pair to switch simultaneously. if the output signals driving the pins are from iob flip-flops, they are synchronous. if the signals driving the pins are from internal logic, they are asynchronous, and therefore more care must be taken that they are simultaneous. any differ- ential pairs can be used for synchronous input and output signals as well as asynchronous input signals. however, only the differential pairs with the _y or _yy suffix can be used for asynchronous output signals. asynchronous output pad name designation because of differences between densities, the differential pairs that can be used for asynchronous outputs vary by device. the pairs that are available in all densities for a given package have the _yy suffix. these pins should be used for differential asynchronous outputs if the design may later move to a different density. all other differential pairs that can be used for asynchronous outputs have the _y suf- fix. to simplify the following tables, the "pad name" column shows the part of the name that is common across densi- ties. the "pad name" column leaves out the _y suffix and the "lvds asynchronous output option" column indicates the densities that allow asynchronous outputs for lvds or lvpecl on the given pin. dll pins pins labeled "i/o (dll)" can be used as general-purpose i/o or as inputs to the dll. adjacent dll pins form a differ- ential pair. they reside in two different banks, so if they are outputs the v cco level must be the same for both banks. each dll pin can also be paired with the adjacent gck clock pin for a differential clock input. the "i/o (dll)" pin always becomes the n terminal when paired with gck, even if it is labeled "p" for its pairing with the adjacent dll pin. vref pins pins labeled "i/o, vref" can be used as either an i/o or a vref pin. if any i/o pin within the bank requires a vref input, all the vref pins in the bank must be connected to the same voltage. see the i/o banking rules in module 2, functional description for more detail. if no pin in a given bank requires vref, then that bank's vref pins can be used as general i/o. to simplify the following tables, the "pad name" column shows the part of the name that is common across densi- ties. when vref is only available in limited densities, the "pad name" column leaves out the vref designation and the "vref option" column indicates the densities that pro- vide vref on the given pin. available differential pairs according to package type device tq144 pq208 ft256 fg456 fg676 xc2s50e 28 50 83 - - xc2s100e 28 50 83 86 - xc2s150e - 50 83 114 - XC2S200E - 50 83 120 - xc2s300e - 50 83 120 - xc2s400e - - 83 120 172 xc2s600e - - - 120 205
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 4 1-800-255-7778 product specification r pinout tables the following device-specific pinout tables include all pack- ages available for each spartan-iie device. they follow the pad locations around the die. in the tq144 package, all vcco pins must be connected to the same voltage. tq144 pinouts (xc2s50e and xc2s100e) pad name pin lv d s async. output option v ref option function bank gnd - p1 - - tms - p2 - - i/o 7 p3 - - i/o 7 p4 - - i/o, vref bank 7 7 p5 - all i/o 7 p6 - - i/o, l27p 7 p7 xc2s50e xc2s100e i/o, l27n 7 p8 xc2s50e - gnd - p9 - - i/o, l26p_yy 7 p10 all - i/o, l26n_yy 7 p11 all - i/o, vref bank 7, l25p 7 p12 xc2s50e all i/o, l25n 7 p13 xc2s50e - i/o 7 p14 - - i/o (irdy) 7 p15 - - gnd - p16 - - vcco - p17 - - i/o (trdy) 6 p18 - - vccint - p19 - - i/o 6 p20 - - i/o, l24p 6 p21 xc2s50e - i/o, vref bank 6, l24n 6 p22 xc2s50e all i/o, l23p_yy 6 p23 all - i/o, l23n_yy 6 p24 all - gnd - p25 - - i/o, l22p 6 p26 xc2s50e - i/o, l22n 6 p27 xc2s50e xc2s100e i/o 6 p28 - - i/o, vref bank 6 6 p29 - all i/o 6 p30 - - i/o, l21p_yy 6 p31 all - i/o, l21n_yy 6 p32 all - m1 - p33 - - gnd - p34 - - m0 - p35 - - vcco - p36 - - m2 - p37 - - i/o, l20n_yy 5 p38 all - i/o, l20p_yy 5 p39 all - i/o 5 p40 - - i/o, vref bank 5 5 p41 - all i/o 5 p42 - - i/o, l19n_yy 5 p43 all xc2s100e i/o, l19p_yy 5 p44 all - gnd - p45 - - vccint - p46 - - i/o, l18n_yy 5 p47 all - i/o, l18p_yy 5 p48 all - i/o, vref bank 5 5 p49 - all i/o (dll), l17n 5 p50 - - vccint - p51 - - gck1, i 5 p52 - - vcco 5 p53 - - gnd - p54 - - gck0, i 4 p55 - - i/o (dll), l17p 4 p56 - - tq144 pinouts (xc2s50e and xc2s100e) (continued) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 5 r i/o 4 p57 - - i/o, vref bank 4 4 p58 - all i/o, l16n_yy 4 p59 all - i/o, l16p_yy 4 p60 all - vccint - p61 - - gnd - p62 - - i/o, l15n_yy 4 p63 all - i/o, l15p_yy 4 p64 all xc2s100e i/o 4 p65 - - i/o, vref bank 4 4 p66 - all i/o 4 p67 - - i/o, l14n_yy 4 p68 all - i/o, l14p_yy 4 p69 all - gnd - p70 - - done 3 p71 - - vcco - p72 - - program - p73 - - i/o (init ), l13n_yy 3 p74 all - i/o (d7), l13p_yy 3 p75 all - i/o 3 p76 - - i/o, vref bank 3 3 p77 - all i/o 3 p78 - - i/o, l12n 3 p79 xc2s50e xc2s100e i/o (d6), l12p 3 p80 xc2s50e - gnd - p81 - - i/o (d5), l11n_yy 3 p82 all - i/o, l11p_yy 3 p83 all - i/o 3 p84 - - tq144 pinouts (xc2s50e and xc2s100e) (continued) pad name pin lv d s async. output option v ref option function bank i/o, vref bank 3, l10n 3 p85 xc2s50e all i/o (d4), l10p 3 p86 xc2s50e - i/o 3 p87 - - vccint - p88 - - i/o (trdy) 3 p89 - - vcco - p90 - - gnd - p91 - - i/o (irdy) 2 p92 - - i/o 2 p93 - - i/o (d3), l9n 2 p94 xc2s50e - i/o, vref bank 2, l9p 2 p95 xc2s50e all i/o 2 p96 - - i/o, l8n_yy 2 p97 all - i/o (d2), l8p_yy 2 p98 all - gnd - p99 - - i/o (d1), l7n 2 p100 xc2s50e - i/o, l7p 2 p101 xc2s50e xc2s100e i/o 2 p102 - - i/o, vref bank 2 2 p103 - all i/o 2 p104 - - i/o (din, d0), l6n_yy 2 p105 all - i/o (dout, busy), l6p_yy 2 p106 all - cclk 2 p107 - - vcco - p108 - - tdo 2 p109 - - gnd - p110 - - tdi - p111 - - tq144 pinouts (xc2s50e and xc2s100e) (continued) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 6 1-800-255-7778 product specification r i/o (cs ), l5p_yy 1 p112 all - i/o (write ), l5n_yy 1 p113 all - i/o 1 p114 - - i/o, vref bank 1 1 p115 - all i/o 1 p116 - - i/o, l4p_yy 1 p117 all xc2s100e i/o, l4n_yy 1 p118 all - gnd - p119 - - vccint - p120 - - i/o, l3p_yy 1 p121 all - i/o, l3n_yy 1 p122 all - i/o, vref bank 1 1 p123 - all i/o 1 p124 - - i/o (dll), l2p 1 p125 - - gck2, i 1 p126 - - gnd - p127 - - vcco - p128 - - gck3, i 0 p129 - - vccint - p130 - - i/o (dll), l2n 0 p131 - - i/o, vref bank 0 0 p132 - all i/o, l1p_yy 0 p133 all - i/o, l1n_yy 0 p134 all - vccint - p135 - - gnd - p136 - - i/o, l0p_yy 0 p137 all - i/o, l0n_yy 0 p138 all xc2s100e tq144 pinouts (xc2s50e and xc2s100e) (continued) pad name pin lv d s async. output option v ref option function bank i/o 0 p139 - - i/o, vref bank 0 0 p140 - all i/o 0 p141 - - i/o 0 p142 - - tck - p143 - - vcco - p144 - - tq144 differential clock pins clock bank p n pin name pin name gck0 4 p55 gck0, i p56 i/o (dll), l17p gck1 5 p52 gck1, i p50 i/o (dll), l17n gck2 1 p126 gck2, i p125 i/o (dll), l2p gck3 0 p129 gck3, i p131 i/o (dll), l2n tq144 pinouts (xc2s50e and xc2s100e) (continued) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 7 r in the pq208 package, all vcco pins must be connected to the same voltage. pq208 pinouts (xc2s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e) pad name pin lv d s async. output option v ref option function bank gnd - p1 - - tms - p2 - - i/o 7 p3 - - i/o 7 p4 - XC2S200E, 300e i/o 7 p5 - - i/o, vref bank 7, l49p 7 p6 xc2s50e, 150e, 200e, 300e all i/o, l49n 7 p7 xc2s50e, 150e, 200e, 300e - i/o 7 p8 - - i/o 7 p9 - - i/o, l48p 7 p10 xc2s50e, 300e xc2s100e, 150e, 200e, 300e i/o, l48n 7 p11 xc2s50e, 300e - gnd - p12 - - vcco - p13 - - vccint - p14 - - i/o, l47p_yy 7 p15 all - i/o, l47n_yy 7 p16 all - i/o, l46p_yy 7 p17 all - i/o, l46n_yy 7 p18 all - gnd - p19 - - i/o, vref bank 7, l45p 7 p20 xc2s50e, 300e all i/o, l45n 7 p21 xc2s50e, 300e - i/o 7 p22 - - i/o, l44p_yy 7 p23 all - i/o (irdy), l44n_yy 7 p24 all - gnd - p25 - - vcco - p26 - - i/o (trdy) 6 p27 - - vccint - p28 - - i/o 6 p29 - - i/o, l43p 6 p30 xc2s50e, 300e - i/o, vref bank 6, l43n 6 p31 xc2s50e, 300e all gnd - p32 - - i/o, l42p_yy 6 p33 all - i/o, l42n_yy 6 p34 all - i/o, l41p_yy 6 p35 all - i/o, l41n_yy 6 p36 all - vccint - p37 - - vcco - p38 - - gnd - p39 - - i/o, l40p 6 p40 xc2s50e, 300e - i/o, l40n 6 p41 xc2s50e, 300e xc2s100e, 150e, 200e, 300e i/o 6 p42 - - i/o 6 p43 - - i/o 6 p44 - - pq208 pinouts (xc2s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 8 1-800-255-7778 product specification r i/o, vref bank 6, l39p 6 p45 xc2s100e, 150e all i/o, l39n 6 p46 xc2s100e, 150e - i/o 6 p47 - XC2S200E, 300e i/o, l38p_yy 6 p48 all - i/o, l38n_yy 6 p49 all - m1 - p50 - - gnd - p51 - - m0 - p52 - - vcco - p53 - - m2 - p54 - - i/o, l37n_yy 5 p55 all - i/o, l37p_yy 5 p56 all - i/o 5 p57 - XC2S200E, 300e i/o 5 p58 - - i/o, vref bank 5, l36n_yy 5 p59 all all i/o, l36p_yy 5 p60 all - i/o, l35n 5 p61 xc2s50e, 100e, 300e - i/o, l35p 5 p62 xc2s50e, 100e, 300e - i/o, l34n 5 p63 xc2s50e, 100e, 200e, 300e xc2s100e, 150e, 200e, 300e i/o, l34p 5 p64 xc2s50e, 100e, 200e, 300e - gnd - p65 - - pq208 pinouts (xc2s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e) pad name pin lv d s async. output option v ref option function bank vcco - p66 - - vccint - p67 - - i/o, l33n 5 p68 xc2s50e, 100e, 200e, 300e - i/o, l33p 5 p69 xc2s50e, 100e, 200e, 300e - i/o 5 p70 - - i/o, l32n 5 p71 xc2s100e, 150e - gnd - p72 - - i/o, vref bank 5, l32p 5 p73 xc2s100e, 150e all i/o 5 p74 - - i/o (dll), l31n 5 p75 - - vccint - p76 - - gck1, i 5 p77 - - vcco - p78 - - gnd - p79 - - gck0, i 4 p80 - - i/o (dll), l31p 4 p81 - - i/o 4 p82 - - i/o, l30n 4 p83 xc2s50e, 200e, 300e - i/o, vref bank 4, l30p 4 p84 xc2s50e, 200e, 300e all gnd - p85 - - i/o, l29n 4 p86 xc2s50e, 200e, 300e - i/o, l29p 4 p87 xc2s50e, 200e, 300e - i/o, l28n 4 p88 xc2s50e, 100e, 200e, 300e - pq208 pinouts (xc2s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 9 r i/o, l28p 4 p89 xc2s50e, 100e, 200e, 300e - vccint - p90 - - vcco - p91 - - gnd - p92 - - i/o, l27n 4 p93 xc2s50e, 100e, 200e, 300e - i/o, l27p 4 p94 xc2s50e, 100e, 200e, 300e xc2s100e, 150e, 200e, 300e i/o 4 p95 - - i/o 4 p96 - - i/o, l26n_yy 4 p97 all - i/o, vref bank 4, l26p_yy 4 p98 all all i/o 4 p99 - - i/o 4 p100 - XC2S200E, 300e i/o, l25n_yy 4 p101 all - i/o, l25p_yy 4 p102 all - gnd - p103 - - done 3 p104 - - vcco - p105 - - program - p106 - - i/o (init ), l24n_yy 3 p107 all - i/o (d7), l24p_yy 3 p108 all - i/o 3 p109 - XC2S200E, 300e i/o 3 p110 - - pq208 pinouts (xc2s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e) pad name pin lv d s async. output option v ref option function bank i/o, vref bank 3, l23n 3 p111 xc2s50e, 150e, 200e, 300e all i/o, l23p 3 p112 xc2s50e, 150e, 200e, 300e - i/o 3 p113 - - i/o 3 p114 - - i/o, l22n 3 p115 xc2s50e, 300e xc2s100e, 150e, 200e, 300e i/o (d6), l22p 3 p116 xc2s50e, 300e - gnd - p117 - - vcco - p118 - - vccint - p119 - - i/o (d5), l21n_yy 3 p120 all - i/o, l21p_yy 3 p121 all - i/o, l20n_yy 3 p122 all - i/o, l20p_yy 3 p123 all - gnd - p124 - - i/o, vref bank 3, l19n 3 p125 xc2s50e, 300e all i/o (d4), l19p 3 p126 xc2s50e, 300e - i/o 3 p127 - - vccint - p128 - - i/o (trdy) 3 p129 - - vcco - p130 - - gnd - p131 - - i/o (irdy), l18n_yy 2 p132 all - i/o, l18p_yy 2 p133 all - pq208 pinouts (xc2s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 10 1-800-255-7778 product specification r i/o 2 p134 - - i/o (d3), l17n 2 p135 xc2s50e, 300e - i/o, vref bank 2, l17p 2 p136 xc2s50e, 300e all gnd - p137 - - i/o, l16n_yy 2 p138 all - i/o, l16p_yy 2 p139 all - i/o, l15n_yy 2 p140 all - i/o (d2), l15p_yy 2 p141 all - vccint - p142 - - vcco - p143 - - gnd - p144 - - i/o (d1), l14n 2 p145 xc2s50e, 300e - i/o, l14p 2 p146 xc2s50e, 300e xc2s100e, 150e, 200e, 300e i/o 2 p147 - - i/o 2 p148 - - i/o 2 p149 - - i/o, vref bank 2, l13n 2 p150 xc2s100e, 150e all i/o, l13p 2 p151 xc2s100e, 150e - i/o 2 p152 - XC2S200E, 300e i/o (din, d0), l12n_yy 2 p153 all - i/o (dout, busy), l12p_yy 2 p154 all - cclk 2 p155 - - pq208 pinouts (xc2s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e) pad name pin lv d s async. output option v ref option function bank vcco - p156 - - tdo 2 p157 - - gnd - p158 - - tdi - p159 - - i/o (cs ), l11p_yy 1 p160 all - i/o (write ), l11n_yy 1 p161 all - i/o 1 p162 - XC2S200E, 300e i/o 1 p163 - - i/o, vref bank 1, l10p_yy 1 p164 all all i/o, l10n_yy 1 p165 all - i/o 1 p166 - - i/o 1 p167 - - i/o, l9p 1 p168 xc2s50e, 100e, 200e, 300e xc2s100e, 150e, 200e, 300e i/o, l9n 1 p169 xc2s50e, 100e, 200e, 300e - gnd - p170 - - vcco - p171 - - vccint - p172 - - i/o, l8p 1 p173 xc2s50e, 100e, 200e, 300e - i/o, l8n 1 p174 xc2s50e, 100e, 200e, 300e - i/o, l7p 1 p175 xc2s50e, 200e, 300e - i/o, l7n 1 p176 xc2s50e, 200e, 300e - gnd - p177 - - pq208 pinouts (xc2s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 11 r i/o, vref bank 1, l6p 1 p178 xc2s50e, 200e, 300e all i/o, l6n 1 p179 xc2s50e, 200e, 300e - i/o 1 p180 - - i/o (dll), l5p 1 p181 - - gck2, i 1 p182 - - gnd - p183 - - vcco - p184 - - gck3, i 0 p185 - - vccint - p186 - - i/o (dll), l5n 0 p187 - - i/o, l4p 0 p188 xc2s50e, 200e, 300e - i/o, vref bank 0, l4n 0 p189 xc2s50e, 200e, 300e all gnd - p190 - - i/o, l3p 0 p191 xc2s50e, 200e, 300e - i/o, l3n 0 p192 xc2s50e, 200e, 300e - i/o, l2p 0 p193 xc2s50e, 100e, 200e, 300e - i/o, l2n 0 p194 xc2s50e, 100e, 200e, 300e - vccint - p195 - - vcco - p196 - - gnd - p197 - - i/o, l1p 0 p198 xc2s50e, 100e, 200e, 300e - i/o, l1n 0 p199 xc2s50e, 100e, 200e, 300e xc2s100e, 150e, 200e, 300e i/o 0 p200 - - pq208 pinouts (xc2s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e) pad name pin lv d s async. output option v ref option function bank i/o 0 p201 - - i/o, l0p_yy 0 p202 all - i/o, vref bank 0, l0n_yy 0 p203 all all i/o 0 p204 - - i/o 0 p205 - XC2S200E, 300e i/o 0 p206 - - tck - p207 - - vcco - p208 - - pq208 differential clock pins clock bank p n pin name pin name gck0 4 p80 gck0, i p81 i/o (dll), l31p gck1 5 p77 gck1, i p75 i/o (dll), l31n gck2 1 p182 gck2, i p181 i/o (dll), l5p gck3 0 p185 gck3, i p187 i/o (dll), l5n pq208 pinouts (xc2s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 12 1-800-255-7778 product specification r ft256 pinouts (xc2 s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e, xc2s400e) pad name pin lv d s async. output option v ref option function bank tms - b1 - - i/o 7 d3 - - i/o, l83p 7 c2 xc2s100e, 150e - i/o, l83n 7 c1 xc2s100e, 150e XC2S200E, 300e, 400e i/o, l82p_yy 7 d2 all - i/o, l82n_yy 7 d1 all - i/o, vref bank 7, l81p 7 e3 xc2s50e, 150e, 200e, 300e, 400e all i/o, l81n 7 e4 xc2s50e, 150e, 200e, 300e, 400e - i/o, l80p 7 e2 XC2S200E, 400e - i/o, l80n 7 e1 XC2S200E, 400e - i/o, l79p 7 f4 xc2s50e, 300e, 400e xc2s100e, 150e, 200e, 300e, 400e i/o, l79n 7 f3 xc2s50e, 300e, 400e - i/o, l78p_yy 7 f2 all - i/o, l78n_yy 7 f1 all - i/o, l77p 7 f5 xc2s100e, 150e - i/o, l77n 7 g5 xc2s100e, 150e - i/o, l76p_yy 7 g3 all - i/o, l76n_yy 7 g4 all - i/o, vref bank 7, l75p 7 g2 xc2s50e, 300e, 400e all i/o, l75n 7 g1 xc2s50e, 300e, 400e - i/o, l74p 7 h4 xc2s100e, 150e, 200e - i/o, l74n 7 h3 xc2s100e, 150e, 200e xc2s400e i/o, l73p_yy 7 h2 all - i/o (irdy), l73n_yy 7 h1 all - i/o (trdy) 6 j4 - - i/o, l72p 6 j2 xc2s100e, 150e, 200e, 400e xc2s400e i/o, l72n 6 j3 xc2s100e, 150e, 200e, 400e - i/o, l71p 6 j1 xc2s50e, 300e, 400e - i/o, vref bank 6, l71n 6 k1 xc2s50e, 300e, 400e all i/o, l70p_yy 6 k2 all - i/o, l70n_yy 6 k3 all - i/o, l69p 6 l1 xc2s100e, 150e, 400e - i/o, l69n 6 l2 xc2s100e, 150e, 400e - i/o, l68p_yy 6 k4 all - i/o, l68n_yy 6 k5 all - i/o, l67p 6 l3 xc2s50e, 300e, 400e - i/o, l67n 6 m2 xc2s50e, 300e, 400e xc2s100e, 150e, 200e, 300e, 400e i/o, l66p 6 m1 xc2s150e, 200e, 400e - i/o, l66n 6 n1 xc2s150e, 200e, 400e - ft256 pinouts (xc2 s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e, xc2s400e) (continued) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 13 r i/o, l65p 6 l4 xc2s50e, 150e, 200e, 300e, 400e - i/o, vref bank 6, l65n 6 l5 xc2s50e, 150e, 200e, 300e, 400e all i/o, l64p_yy 6 m3 all - i/o, l64n_yy 6 m4 all - i/o, l63p 6 n2 xc2s100e, 200e, 300e - i/o, l63n 6 n3 xc2s100e, 200e, 300e XC2S200E, 300e, 400e i/o, l62p_yy 6 p1 all - i/o, l62n_yy 6 p2 all - m1 - r1 - - m0 - t2 - - m2 - r3 - - i/o, l61n_yy 5 p4 all - i/o, l61p_yy 5 r4 all - i/o, l60n 5 t3 xc2s50e, 100e, 200e, 300e, 400e XC2S200E, 300e, 400e i/o, l60p 5 t4 xc2s50e, 100e, 200e, 300e, 400e - i/o, l59n_yy 5 n5 all - i/o, l59p_yy 5 p5 all - i/o, vref bank 5, l58n_yy 5 r5 all all i/o, l58p_yy 5 t5 all - i/o, l57n 5 n6 xc2s50e, 100e, 150e, 300e - ft256 pinouts (xc2s5 0e, xc2s100e, xc2s150e, XC2S200E, xc2s300e, xc2s400e) (continued) pad name pin lv d s async. output option v ref option function bank i/o, l57p 5 p6 xc2s50e, 100e, 150e, 300e - i/o, l56n 5 r6 xc2s50e, 100e, 200e, 300e, 400e xc2s100e, 150e, 200e, 300e, 400e i/o, l56p 5 t6 xc2s50e, 100e, 200e, 300e, 400e - i/o, l55n 5 m6 xc2s50e, 100e, 200e, 300e, 400e - i/o, l55p 5 n7 xc2s50e, 100e, 200e, 300e, 400e - i/o 5 p7 - - i/o, l54n 5 r7 xc2s50e, 200e, 300e, 400e - i/o, l54p 5 t7 xc2s50e, 200e, 300e, 400e - i/o, vref bank 5, l53n 5 m7 xc2s50e, 200e, 300e, 400e all i/o, l53p 5 n8 xc2s50e, 200e, 300e, 400e - i/o 5 p8 - xc2s400e i/o (dll), l52n 5 r8 - - gck1, i 5 t8 - - gck0, i 4 t9 - - i/o (dll), l52p 4 r9 - - i/o, l51n 4 p9 xc2s50e, 150e, 200e, 400e xc2s400e ft256 pinouts (xc2 s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e, xc2s400e) (continued) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 14 1-800-255-7778 product specification r i/o, l51p 4 n9 xc2s50e, 150e, 200e, 400e - i/o, l50n 4 t10 xc2s50e, 200e, 300e, 400e - i/o, vref bank 4, l50p 4 r10 xc2s50e, 200e, 300e, 400e all i/o, l49n 4 p10 xc2s50e, 200e, 300e, 400e - i/o, l49p 4 r11 xc2s50e, 200e, 300e, 400e - i/o 4 t11 - - i/o, l48n 4 n10 xc2s50e, 100e, 200e, 300e, 400e - i/o, l48p 4 m10 xc2s50e, 100e, 200e, 300e, 400e - i/o, l47n 4 p11 xc2s50e, 100e, 200e, 300e, 400e - i/o, l47p 4 r12 xc2s50e, 100e, 200e, 300e, 400e xc2s100e, 150e, 200e, 300e, 400e i/o, l46n 4 t12 xc2s50e, 100e, 150e, 300e - i/o, l46p 4 t13 xc2s50e, 100e, 150e, 300e - i/o, l45n_yy 4 n11 all - i/o, vref bank 4, l45p_yy 4 m11 all all i/o, l44n_yy 4 p12 all - i/o, l44p_yy 4 n12 all - ft256 pinouts (xc2 s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e, xc2s400e) (continued) pad name pin lv d s async. output option v ref option function bank i/o, l43n 4 r13 xc2s50e, 150e XC2S200E, 300e, 400e i/o, l43p 4 p13 xc2s50e, 150e - i/o, l42n_yy 4 t14 all - i/o, l42p_yy 4 r14 all - done 3 t15 - - program - r16 - - i/o (init ), l41n_yy 3 p15 all - i/o (d7), l41p_yy 3 p16 all - i/o, l40n 3 n15 xc2s100e, 150e, 400e - i/o, l40p 3 n16 xc2s100e, 150e, 400e XC2S200E, 300e, 400e i/o, l39n 3 n14 xc2s50e, 100e, 150e, 200e, 300e (1) - i/o, l39p 3 m14 xc2s50e, 100e, 150e, 200e, 300e (1) - i/o, vref bank 3, l38n 3 m15 xc2s50e, 150e, 200e, 300e, 400e all i/o, l38p 3 m16 xc2s50e, 150e, 200e, 300e, 400e - i/o (2) 3 m13 - - i/o (2) 3 l14 - - i/o, l36n 3 l15 xc2s50e, 300e, 400e xc2s100e, 150e, 200e, 300e, 400e i/o (d6), l36p 3 l16 xc2s50e, 300e, 400e - ft256 pinouts (xc2 s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e, xc2s400e) (continued) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 15 r i/o (d5), l35n_yy 3 l13 all - i/o, l35p_yy 3 k14 all - i/o, l34n 3 k15 xc2s100e, 150e, 400e - i/o, l34p 3 k16 xc2s100e, 150e, 400e - i/o, l33n 3 l12 xc2s50e, 100e, 150e, 200e, 300e (1) - i/o, l33p 3 k12 xc2s50e, 100e, 150e, 200e, 300e (1) - i/o, vref bank 3, l32n 3 k13 xc2s50e, 300e, 400e all i/o (d4), l32p 3 j14 xc2s50e, 300e, 400e - i/o, l31n 3 j15 xc2s100e, 150e, 200e, 400e - i/o, l31p 3 j16 xc2s100e, 150e, 200e, 400e xc2s400e i/o (trdy) 3 j13 - - i/o (irdy), l30n_yy 2 h16 all - i/o, l30p_yy 2 g16 all - i/o, l29n 2 h14 xc2s100e, 150e, 200e, 400e xc2s400e i/o, l29p 2 h15 xc2s100e, 150e, 200e, 400e - i/o (d3), l28n 2 g15 xc2s50e, 300e, 400e - ft256 pinouts (xc2s5 0e, xc2s100e, xc2s150e, XC2S200E, xc2s300e, xc2s400e) (continued) pad name pin lv d s async. output option v ref option function bank i/o, vref bank 2, l28p 2 f16 xc2s50e, 300e, 400e all i/o, l27n 2 h13 xc2s50e, 100e, 150e, 200e, 300e (1) - i/o, l27p 2 g14 xc2s50e, 100e, 150e, 200e, 300e (2) - i/o, l26n 2 f15 xc2s100e, 150e, 400e - i/o, l26p 2 e16 xc2s100e, 150e, 400e - i/o, l25n_yy 2 g13 all - i/o (d2), l25p_yy 2 f14 all - i/o (d1), l24n 2 e15 xc2s50e, 300e, 400e - i/o, l24p 2 d16 xc2s50e, 300e, 400e xc2s100e, 150e, 200e, 300e, 400e i/o, l23n 2 f13 xc2s150e, 200e, 400e - i/o, l23p 2 e14 xc2s150e, 200e, 400e - i/o, l22n 2 d15 xc2s50e, 150e, 200e, 300e, 400e - i/o, vref bank 2, l22p 2 c16 xc2s50e, 150e, 200e, 300e, 400e all i/o, l21n 2 g12 xc2s50e, 100e, 200e, 300e - i/o, l21p 2 f12 xc2s50e, 100e, 200e, 300e - i/o, l20n 2 e13 xc2s100e, 200e, 300e - ft256 pinouts (xc2 s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e, xc2s400e) (continued) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 16 1-800-255-7778 product specification r i/o, l20p 2 d14 xc2s100e, 200e, 300e XC2S200E, 300e, 400e i/o (din, d0), l19n_yy 2 b16 all - i/o (dout, busy), l19p_yy 2 c15 all - cclk 2 a15 - - tdo 2 b14 - - tdi - c13 - - i/o (cs ), l18p_yy 1 a14 all - i/o (write ), l18n_yy 1 a13 all - i/o, l17p 1 b13 xc2s50e, 100e, 200e, 300e, 400e XC2S200E, 300e, 400e i/o, l17n 1 c12 xc2s50e, 100e, 200e, 300e, 400e - i/o, l16p_yy 1 b12 all - i/o, l16n_yy 1 a12 all - i/o, vref bank 1, l15p_yy 1 d12 all all i/o, l15n_yy 1 e11 all - i/o, l14p 1 d11 xc2s50e, 100e, 150e, 300e - i/o, l14n 1 c11 xc2s50e, 100e, 150e, 300e - i/o, l13p 1 b11 xc2s50e, 100e, 200e, 300e, 400e xc2s100e, 150e, 200e, 300e, 400e i/o, l13n 1 a11 xc2s50e, 100e, 200e, 300e, 400e - ft256 pinouts (xc2 s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e, xc2s400e) (continued) pad name pin lv d s async. output option v ref option function bank i/o, l12p 1 e10 xc2s50e, 100e, 200e, 300e, 400e - i/o, l12n 1 d10 xc2s50e, 100e, 200e, 300e, 400e - i/o 1 c10 - - i/o, l11p 1 b10 xc2s50e, 200e, 300e, 400e - i/o, l11n 1 a10 xc2s50e, 200e, 300e, 400e - i/o, vref bank 1, l10p 1 d9 xc2s50e, 200e, 300e, 400e all i/o, l10n 1 c9 xc2s50e, 200e, 300e, 400e - i/o, l9p 1 b9 xc2s50e, 150e, 200e, 400e - i/o, l9n 1 a9 xc2s50e, 150e, 200e, 400e xc2s400e i/o (dll), l8p 1 a8 - - gck2, i 1 b8 - - gck3, i 0 c8 - - i/o (dll), l8n 0 d8 - - i/o 0 a7 - xc2s400e i/o, l7p 0 e7 xc2s50e, 200e, 300e, 400e - i/o, vref bank 0, l7n 0 d7 xc2s50e, 200e, 300e, 400e all ft256 pinouts (xc2 s50e, xc2s100e, xc2s150e, XC2S200E, xc2s300e, xc2s400e) (continued) pad name pin lv d s async. output option v ref option function bank
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 17 r i/o, l6p 0 c7 xc2s50e, 200e, 300e, 400e - i/o, l6n 0 b7 xc2s50e, 200e, 300e, 400e - i/o 0 a6 - - i/o, l5p 0 b6 xc2s50e, 100e, 200e, 300e, 400e - i/o, l5n 0 c6 xc2s50e, 100e, 200e, 300e, 400e - i/o, l4p 0 a5 xc2s50e, 100e, 200e, 300e, 400e - i/o, l4n 0 b5 xc2s50e, 100e, 200e, 300e, 400e xc2s100e, 150e, 200e, 300e, 400e i/o, l3p 0 d6 xc2s50e, 100e, 300e - i/o, l3n 0 e6 xc2s50e, 100e, 300e - i/o, l2p_yy 0 d5 all - i/o, vref bank 0, l2n_yy 0 c5 all all i/o, l1p_yy 0 b4 all - i/o, l1n_yy 0 c4 all - i/o, l0p_yy 0 a4 all - i/o, l0n_yy 0 a3 all XC2S200E, 300e, 400e i/o 0 b3 - - tck - a2 - - notes: 1. although designated with the _yy suffix in the xc2s50e, xc2s100e, xc2s150e, XC2S200E, and xc2s300e, these differential pairs are not asynchronous in the xc2s400e. 2. there is no pair l37. ft256 pinouts (xc2s5 0e, xc2s100e, xc2s150e, XC2S200E, xc2s300e, xc2s400e) (continued) pad name pin lv d s async. output option v ref option function bank ft256 differential clock pins clock bank p n pin name pin name gck0 4 t9 gck0, i r9 i/o (dll), l52p gck1 5 t8 gck1, i r8 i/o (dll), l52n gck2 1 b8 gck2, i a8 i/o (dll), l8p gck3 0 c8 gck3, i d8 i/o (dll), l8n additional ft256 package pins vccint pins c3 c14 d4 d13 e5 e12 m5 m12 n4 n13 p3 p14 - - - vcco bank 0 pins e8 f7 f8 - - vcco bank 1 pins e9 f9 f10 - - vcco bank 2 pins g11 h11 h12 - - vcco bank 3 pins j11 j12 k11 - - vcco bank 4 pins l9 l10 m9 - - vcco bank 5 pins l7 l8 m8 - - vcco bank 6 pins j5 j6 k6 - - vcco bank 7 pins g6 h5 h6 - - gnd pins a1 a16 b2 b15 f6 f11 g7 g8 g9 g10 h7 h8 h9 h10 j7 j8 j9 j10 k7 k8 k9 k10 l6 l11 r2 r15 t1 t16 - -
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 18 1-800-255-7778 product specification r fg456 pinouts (xc2s100e, xc2s150e, xc2s 200e, xc2s300e, xc 2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e tms - e4 - - tms tms tms tms tms tms i/o 7 d3 xc2s150e - i/o i/o, l113p_y i/o i/o i/o i/o i/o 7 c2 - - - - - i/o i/o i/o i/o 7 c1 xc2s150e - - i/o, l113n_y i/o i/o i/o i/o i/o, l#p_y 7 d2 xc2s150e, 200e, 300e, 400e - - i/o, l112p_y i/o, l119p_y i/o, l119p_y i/o, l119p_y i/o, l119p i/o, l#n_y 7 d1 xc2s150e, 200e, 300e, 400e - i/o i/o, l112n_y i/o, l119n_y i/o, l119n_y i/o, l119n_y i/o, l119n i/o, l#p_y 7 e2 xc2s100e, 200e, 300e, 600e XC2S200E, 300e, 400e, 600e i/o, l85p_y i/o, l111p i/o, vref bank 7, l118p_y i/o, vref bank 7, l118p_y i/o, vref bank 7, l118p i/o, vref bank 7, l118p_y i/o, l#n_y 7 e3 xc2s100e, 200e, 300e, 600e - i/o, l85n_y i/o, l111n i/o, l118n_y i/o, l118n_y i/o, l118n i/o, l118n_y i/o 7 e1 - - - - - i/o i/o i/o i/o 7 f5 - - - i/o i/o i/o i/o i/o i/o, l#p_y 7 f4 xc2s100e, 200e, 300e, 600e - i/o, l84p_y i/o, l110p i/o, l117p_y i/o, l117p_y i/o, l117p i/o, l117p_y i/o, l#n_y 7 f3 xc2s100e, 200e, 300e, 600e - i/o, l84n_y i/o, l110n i/o, l117n_y i/o, l117n_y i/o, l117n i/o, l117n_y i/o, vref bank 7, l#p_y 7 f2 xc2s150e, 200e, 300e, 400e, 600e all i/o, vref bank 7, l83p i/o, vref bank 7, l109p_y i/o, vref bank 7, l116p_y i/o, vref bank 7, l116p_y i/o, vref bank 7, l116p_y i/o, vref bank 7, l116p_y i/o, l#n_y 7 f1 xc2s150e, 200e, 300e, 400e, 600e - i/o, l83n i/o, l109n_y i/o, l116n_y i/o, l116n_y i/o, l116n_y i/o, l116n_y i/o 7 g5 - - - i/o i/o i/o i/o i/o i/o, l#p_y 7 g4 xc2s150e, 200e, 300e, 400e - - i/o, l108p_y i/o, l115p_y i/o, l115p_y i/o, l115p_y i/o, l115p i/o, l#n_y 7 g3 xc2s150e, 200e, 300e, 400e - i/o i/o, l108n_y i/o, l115n_y i/o, l115n_y i/o, l115n_y i/o, l115n i/o, l#p_y 7 g2 xc2s100e, 150e, 300e, 600e xc2s600e i/o, l82p_y i/o, l107p_y i/o, l114p i/o, l114p_y i/o, l114p i/o, vref bank 7, l114p_y i/o, l#n_y 7 g1 xc2s100e, 150e, 300e, 600e - i/o, l82n_y i/o, l107n_y i/o, l114n i/o, l114n_y i/o, l114n i/o, l114n_y
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 19 r i/o 7 h5 - - - - - i/o i/o i/o i/o, vref bank 7, l#p_y 7 h3 xc2s300e, 400e, 600e all i/o, vref bank 7, l81p i/o, vref bank 7, l106p i/o, vref bank 7, l113p i/o, vref bank 7, l113p_y i/o, vref bank 7, l113p_y i/o, vref bank 7, l113p_y i/o, l#n_y 7 h4 xc2s300e, 400e, 600e - i/o, l81n i/o, l106n i/o, l113n i/o, l113n_y i/o, l113n_y i/o, l113n_y i/o, l#p_yy 7 h2 all - i/o, l80p_yy i/o, l105p_yy i/o, l112p_yy i/o, l112p_yy i/o, l112p_yy i/o, l112p_yy i/o, l#n_yy 7 h1 all - i/o, l80n_yy i/o, l105n_yy i/o, l112n_yy i/o, l112n_yy i/o, l112n_yy i/o, l112n_yy i/o 7 j6 - - - - i/o i/o i/o i/o i/o, l#p_y 7 j4 xc2s150e, 200e, 300e, 400e - - i/o, l104p_y i/o, l111p_y i/o, l111p_y i/o, l111p_y i/o, l111p i/o, l#n_y 7 j5 xc2s100e, 150e, 200e, 300e, 400e - i/o, l79p_y i/o, l104n_y i/o, l111n_y i/o, l111n_y i/o, l111n_y i/o, l111n i/o, l#p_y 7 j3 xc2s100e, 150e, 200e, 300e, 600e - i/o, l79n_y i/o, l103p_y i/o, l110p_y i/o, l110p_y i/o, l110p i/o, l110p_y i/o, l#n_y 7 j2 xc2s150e, 200e, 300e, 600e - - i/o, l103n_y i/o, l110n_y i/o, l110n_y i/o, l110n i/o, l110n_y i/o 7 j1 - - - - i/o i/o i/o i/o i/o, l#p 7 k5 xc2s100e, 150e, 200e, 300e, 600e (1) - i/o, l78p_yy i/o, l102p_yy i/o, l109p_yy i/o, l109p_yy i/o, l109p i/o, l109p_y i/o, l#n 7 k6 xc2s100e, 150e, 200e, 300e, 600e (1) - i/o, l78n_yy i/o, l102n_yy i/o, l109n_yy i/o, l109n_yy i/o, l109n i/o, l109n_y i/o, vref bank 7, l#p_y 7 k3 xc2s300e, 400e, 600e all i/o, vref bank 7, l77p i/o, vref bank 7, l101p i/o, vref bank 7, l108p i/o, vref bank 7, l108p_y i/o, vref bank 7, l108p_y i/o, vref bank 7, l108p_y i/o, l#n_y 7 k4 xc2s300e, 400e, 600e - i/o, l77n i/o, l101n i/o, l108n i/o, l108n_y i/o, l108n_y i/o, l108n_y i/o 7 k2 - - - - - i/o i/o i/o i/o, l#p_y 7 k1 xc2s300e, 400e - - - i/o, l107p i/o, l107p_y i/o, l107p_y i/o, l107p i/o, l#n_y 7 l1 xc2s100e, 150e, 300e, 400e - i/o, l76p_y i/o, l100p_y i/o, l107n i/o, l107n_y i/o, l107n_y i/o, l107n i/o, l#p_y 7 l3 xc2s100e, 150e, 200e, 300e, 600e xc2s400e, 600e i/o, l76n_y i/o, l100n_y i/o, l106p_y i/o, l106p_y i/o, vref bank 7, l106p i/o, vref bank 7, l106p_y i/o, l#n_y 7 l2 XC2S200E, 300e, 600e - - i/o i/o, l106n_y i/o, l106n_y i/o, l106n i/o, l106n_y i/o 7 l4 - - - - - i/o i/o i/o fg456 pinouts (xc2s100e, xc 2s150e, xc2s 200e, xc2s300e, xc2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 20 1-800-255-7778 product specification r i/o, l#p_yy 7 l5 all - i/o, l75p_yy i/o, l99p_yy i/o, l105p_yy i/o, l105p_yy i/o, l105p_yy i/o, l105p_yy i/o (irdy), l#n_yy 7 l6 all - i/o (irdy), l75n_yy i/o (irdy), l99n_yy i/o (irdy), l105n_yy i/o (irdy), l105n_yy i/o (irdy), l105n_yy i/o (irdy), l105n_yy i/o (trdy) 6 m1 - - i/o (trdy) i/o (trdy) i/o (trdy) i/o (trdy) i/o (trdy) i/o (trdy) i/o 6 m2 - - - - - i/o i/o i/o i/o, l#p_y 6 m3 XC2S200E, 300e, 600e - - i/o i/o, l104p_y i/o, l104p_y i/o, l104p i/o, l104p_y i/o, l#n_y 6 m4 xc2s100e, 150e, 200e, 300e, 600e xc2s400e, 600e i/o, l74p_y i/o, l98p_y i/o, l104n_y i/o, l104n_y i/o, vref bank 6, l104n i/o, vref bank 6, l104n_y i/o, l#p_y 6 m5 xc2s100e, 150e, 300e, 400e - i/o, l74n_y i/o, l98n_y i/o, l103p i/o, l103p_y i/o, l103p_y i/o, l103p i/o, l#n_y 6 m6 xc2s300e, 400e - - - i/o, l103n i/o, l103n_y i/o, l103n_y i/o, l103n i/o 6 n1 - - - - - i/o i/o i/o i/o 6 n2 - - i/o, l73p i/o, l97p i/o i/o i/o i/o i/o, vref bank 6, l#p 6 n3 XC2S200E, 400e all i/o, vref bank 6, l73n i/o, vref bank 6, l97n i/o, vref bank 6, l102p_y i/o, vref bank 6, l102p i/o, vref bank 6, l102p_y i/o, vref bank 6, l102p i/o, l#n 6 n4 xc2s100e, 150e, 200e, 400e - i/o, l72p_y i/o, l96p_y i/o, l102n_y i/o, l102n i/o, l102n_y i/o, l102n i/o, l#p_y 6 n5 xc2s100e, 150e, 300e, 600e - i/o, l72n_y i/o, l96n_y i/o, l101p i/o, l101p_y i/o, l101p i/o, l101p_y i/o, l#n_y 6 n6 xc2s300e, 600e - - - i/o, l101n i/o, l101n_y i/o, l101n i/o, l101n_y i/o, l#p_y 6 p1 xc2s150e, 200e, 300e, 600e - - i/o, l95p_y i/o, l100p_y i/o, l100p_y i/o, l100p i/o, l100p_y i/o, l#n_y 6 p2 xc2s100e, 150e, 200e, 300e, 600e - i/o, l71p_y i/o, l95n_y i/o, l100n_y i/o, l100n_y i/o, l100n i/o, l100n_y i/o 6 r1 xc2s100e, 150e - i/o, l71n_y i/o, l94p_y i/o i/o i/o i/o i/o, l#p_y 6 p3 xc2s150e, 200e, 300e, 400e, 600e - - i/o, l94n_y i/o, l99p_y i/o, l99p_y i/o, l99p_y i/o, l99p_y i/o, l#n_y 6 p4 XC2S200E, 300e, 400e, 600e - - - i/o, l99n_y i/o, l99n_y i/o, l99n_y i/o, l99n_y i/o, l#p_yy 6 p5 all - i/o, l70p_yy i/o, l93p_yy i/o, l98p_yy i/o, l98p_yy i/o, l98p_yy i/o, l98p_yy i/o, l#n_yy 6 p6 all - i/o, l70n_yy i/o, l93n_yy i/o, l98n_yy i/o, l98n_yy i/o, l98n_yy i/o, l98n_yy fg456 pinouts (xc2s100e, xc2s150e, xc2s 200e, xc2s300e, xc 2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 21 r i/o, l#p_y 6 r2 xc2s300e, 400e, 600e - i/o, l69p i/o, l92p i/o, l97p i/o, l97p_y i/o, l97p_y i/o, l97p_y i/o, vref bank 6, l#n_y 6 r3 xc2s300e, 400e, 600e all i/o, vref bank 6, l69n i/o, vref bank 6, l92n i/o, vref bank 6, l97n i/o, vref bank 6, l97n_y i/o, vref bank 6, l97n_y i/o, vref bank 6, l97n_y i/o 6 r4 - - - - - i/o i/o i/o i/o 6 r5 - - i/o i/o i/o i/o i/o i/o i/o, l#p 6 t2 XC2S200E, 400e, 600e xc2s600e i/o, l68p i/o, l91p i/o, l96p_y i/o, l96p i/o, l96p_y i/o, vref bank 6, l96p_y i/o, l#n 6 t3 XC2S200E, 400e, 600e - i/o, l68n i/o, l91n i/o, l96n_y i/o, l96n i/o, l96n_y i/o, l96n_y i/o, l#p_y 6 t4 xc2s150e, 300e, 400e - - i/o, l90p_y i/o, l95p i/o, l95p_y i/o, l95p_y i/o, l95p i/o, l#n_y 6 t5 xc2s150e, 300e, 400e - - i/o, l90n_y i/o, l95n i/o, l95n_y i/o, l95n_y i/o, l95n i/o, l#p_y 6 t1 xc2s150e, 200e, 300e, 400e, 600e - i/o, l67p i/o, l89p_y i/o, l94p_y i/o, l94p_y i/o, l94p_y i/o, l94p_y i/o, vref bank 6, l#n_y 6 u1 xc2s150e, 200e, 300e, 400e, 600e all i/o, vref bank 6, l67n i/o, vref bank 6, l89n_y i/o, vref bank 6, l94n_y i/o, vref bank 6, l94n_y i/o, vref bank 6, l94n_y i/o, vref bank 6, l94n_y i/o 6 u2 xc2s100e - i/o, l66p_y i/o i/o i/o i/o i/o i/o, l#p_y 6 u3 xc2s100e, 150e, 200e, 300e, 400e, 600e - i/o, l66n_y i/o, l88p_y i/o, l93p_y i/o, l93p_y i/o, l93p_y i/o, l93p_y i/o, l#n_y 6 u4 xc2s150e, 200e, 300e, 400e, 600e - - i/o, l88n_y i/o, l93n_y i/o, l93n_y i/o, l93n_y i/o, l93n_y i/o 6 v1 - - - - - i/o i/o i/o i/o, l#p_y 6 w1 xc2s100e, 200e, 300e, 600e - i/o, l65p_y i/o, l87p i/o, l92p_y i/o, l92p_y i/o, l92p i/o, l92p_y i/o, l#n_y 6 v2 xc2s100e, 200e, 300e, 600e XC2S200E, 300e, 400e, 600e i/o, l65n_y i/o, l87n i/o, vref bank 6, l92n_y i/o, vref bank 6, l92n_y i/o, vref bank 6, l92n i/o, vref bank 6, l92n_y i/o 6 w2 - - i/o i/o i/o i/o i/o i/o i/o, l#p_y 6 v3 XC2S200E, 300e, 400e - - i/o, l86p i/o, l91p_y i/o, l91p_y i/o, l91p_y i/o, l91p i/o, l#n_y 6 v4 XC2S200E, 300e, 400e - - i/o, l86n i/o, l91n_y i/o, l91n_y i/o, l91n_y i/o, l91n i/o 6 y1 - - - - - i/o i/o i/o i/o, l#p_yy 6 y2 all - i/o, l64p_yy i/o, l85p_yy i/o, l90p_yy i/o, l90p_yy i/o, l90p_yy i/o, l90p_yy i/o, l#n_yy 6 w3 all - i/o, l64n_yy i/o, l85n_yy i/o, l90n_yy i/o, l90n_yy i/o, l90n_yy i/o, l90n_yy m1 - u5 - - m1 m1 m1 m1 m1 m1 fg456 pinouts (xc2s100e, xc 2s150e, xc2s 200e, xc2s300e, xc2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 22 1-800-255-7778 product specification r m0 - aa1 - - m0 m0 m0 m0 m0 m0 m2 - ab2 - - m2 m2 m2 m2 m2 m2 i/o, l#n_y 5 aa3 xc2s150e, 200e, 300e, 400e, 600e - - i/o, l84n_y i/o, l89n_y i/o, l89n_y i/o, l89n_y i/o, l89n_y i/o, l#p_y 5 ab3 xc2s150e, 200e, 300e, 400e, 600e - - i/o, l84p_y i/o, l89p_y i/o, l89p_y i/o, l89p_y i/o, l89p_y i/o 5 ab4 - - - - - i/o i/o i/o i/o 5 aa5 xc2s100e, 150e - i/o, l63n_y i/o, l83n_y i/o i/o i/o i/o i/o, l#n_y 5 w5 xc2s100e, 150e, 200e, 300e, 400e, 600e - i/o, l63p_y i/o, l83p_y i/o, l88n_y i/o, l88n_y i/o, l88n_y i/o, l88n_y i/o, l#p_y 5 y5 XC2S200E, 300e, 400e, 600e - i/o i/o i/o, l88p_y i/o, l88p_y i/o, l88p_y i/o, l88p_y i/o, l#n_y 5 ab5 xc2s100e, 200e, 300e, 400e, 600e XC2S200E, 300e, 400e, 600e i/o, l62n_y i/o, l82n i/o, vref bank 5, l87n_y i/o, vref bank 5, l87n_y i/o, vref bank 5, l87n_y i/o, vref bank 5, l87n_y i/o, l#p_y 5 ab6 xc2s100e, 200e, 300e, 400e, 600e - i/o, l62p_y i/o, l82p i/o, l87p_y i/o, l87p_y i/o, l87p_y i/o, l87p_y i/o 5 y6 - - - - - i/o i/o i/o i/o 5 aa6 - - - i/o i/o i/o i/o i/o i/o, l#n_yy 5 v6 all - i/o, l61n_yy i/o, l81n_yy i/o, l86n_yy i/o, l86n_yy i/o, l86n_yy i/o, l86n_yy i/o, l#p_yy 5 w6 all - i/o, l61p_yy i/o, l81p_yy i/o, l86p_yy i/o, l86p_yy i/o, l86p_yy i/o, l86p_yy i/o, vref bank 5, l#n_yy 5 ab7 all all i/o, vref bank 5, l60n_yy i/o, vref bank 5, l80n_yy i/o, vref bank 5, l85n_yy i/o, vref bank 5, l85n_yy i/o, vref bank 5, l85n_yy i/o, vref bank 5, l85n_yy i/o, l#p_yy 5 aa7 all - i/o, l60p_yy i/o, l80p_yy i/o, l85p_yy i/o, l85p_yy i/o, l85p_yy i/o, l85p_yy i/o 5 y7 - - - i/o i/o i/o i/o i/o i/o, l#n_y 5 v7 xc2s300e, 600e - - i/o, l79n i/o, l84n i/o, l84n_y i/o, l84n i/o, l84n_y i/o, l#p_y 5 w7 xc2s300e, 600e - i/o i/o, l79p i/o, l84p i/o, l84p_y i/o, l84p i/o, l84p_y i/o, l#n_y 5 ab8 xc2s100e, 300e, 600e xc2s600e i/o, l59n_y i/o, l78n i/o, l83n i/o, l83n_y i/o, l83n i/o, vref bank 5, l83n_y i/o, l#p_y 5 aa8 xc2s100e, 300e, 600e - i/o, l59p_y i/o, l78p i/o, l83p i/o, l83p_y i/o, l83p i/o, l83p_y i/o 5 y8 - - - - - i/o i/o i/o fg456 pinouts (xc2s100e, xc2s150e, xc2s 200e, xc2s300e, xc 2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 23 r i/o, vref bank 5, l#n_y 5 v8 xc2s100e, 200e, 300e, 400e, 600e all i/o, vref bank 5, l58n_y i/o, vref bank 5, l77n i/o, vref bank 5, l82n_y i/o, vref bank 5, l82n_y i/o, vref bank 5, l82n_y i/o, vref bank 5, l82n_y i/o, l#p_y 5 w8 xc2s100e, 200e, 300e, 400e, 600e - i/o, l58p_y i/o, l77p i/o, l82p_y i/o, l82p_y i/o, l82p_y i/o, l82p_y i/o, l#n_y 5 ab9 xc2s100e, 200e, 300e, 400e, 600e - i/o, l57n_y i/o, l76n i/o, l81n_y i/o, l81n_y i/o, l81n_y i/o, l81n_y i/o, l#p_y 5 aa9 xc2s100e, 200e, 300e, 400e, 600e - i/o, l57p_y i/o, l76p i/o, l81p_y i/o, l81p_y i/o, l81p_y i/o, l81p_y i/o 5 ab10 - - - - i/o i/o i/o i/o i/o, l#n_y 5 w9 xc2s150e, 300e, 400e, 600e - - i/o, l75n_y i/o, l80n i/o, l80n_y i/o, l80n_y i/o, l80n_y i/o, l#p_y 5 y9 xc2s100e, 150e, 300e, 400e, 600e - i/o, l56n_y i/o, l75p_y i/o, l80p i/o, l80p_y i/o, l80p_y i/o, l80p_y i/o, l#n_y 5 v9 xc2s100e, 150e, 300e, 400e, 600e - i/o, l56p_y i/o, l74n_y i/o, l79n i/o, l79n_y i/o, l79n_y i/o, l79n_y i/o, l#p_y 5 u9 xc2s150e, 300e, 400e, 600e - - i/o, l74p_y i/o, l79p i/o, l79p_y i/o, l79p_y i/o, l79p_y i/o 5 aa10 - - - - i/o i/o i/o i/o i/o, l#n_y 5 w10 XC2S200E, 300e, 400e, 600e - i/o, l55n i/o, l73n i/o, l78n_y i/o, l78n_y i/o, l78n_y i/o, l78n_y i/o, l#p_y 5 y10 XC2S200E, 300e, 400e, 600e - i/o, l55p i/o, l73p i/o, l78p_y i/o, l78p_y i/o, l78p_y i/o, l78p_y i/o, vref bank 5, l#n_y 5 v10 XC2S200E, 300e, 400e, 600e all i/o, vref bank 5, l54n i/o, vref bank 5, l72n i/o, vref bank 5, l77n_y i/o, vref bank 5, l77n_y i/o, vref bank 5, l77n_y i/o, vref bank 5, l77n_y i/o, l#p_y 5 u10 XC2S200E, 300e, 400e, 600e - i/o, l54p i/o, l72p i/o, l77p_y i/o, l77p_y i/o, l77p_y i/o, l77p_y i/o 5 u11 - - - - - i/o i/o i/o i/o 5 v11 - - - - i/o i/o i/o i/o i/o, l#n 5 w11 XC2S200E, 400e - i/o i/o, l71n i/o, l76n_y i/o, l76n i/o, l76n_y i/o, l76n i/o, l#p 5 y11 XC2S200E, 400e xc2s400e, 600e - i/o, l71p i/o, l76p_y i/o, l76p i/o, vref bank 5, l76p_y i/o, vref bank 5, l76p i/o 5 aa11 - - - - - i/o i/o i/o i/o (dll), l#n 5 ab11 - - i/o (dll), l53n i/o (dll), l70n i/o (dll), l75n i/o (dll), l75n i/o (dll), l75n i/o (dll), l75n gck1, i 5 ab12 - - gck1, i gck1, i gck1, i gck1, i gck1, i gck1, i fg456 pinouts (xc2s100e, xc 2s150e, xc2s 200e, xc2s300e, xc2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 24 1-800-255-7778 product specification r gck0, i 4 aa12 - - gck0, i gck0, i gck0, i gck0, i gck0, i gck0, i i/o (dll), l#p 4 y12 - - i/o (dll), l53p i/o (dll), l70p i/o (dll), l75p i/o (dll), l75p i/o (dll), l75p i/o (dll), l75p i/o 4 w12 - - - - - i/o i/o i/o i/o, l#n 4 v12 xc2s150e, 300e, 600e - - i/o, l69n_y i/o, l74n i/o, l74n_y i/o, l74n i/o, l74n_y i/o, l#p 4 u12 xc2s150e, 300e, 600e xc2s400e, 600e i/o, l52n i/o, l69p_y i/o, l74p i/o, l74p_y i/o, vref bank 4, l74p i/o, vref bank 4, l74p_y i/o, l#n 4 ab13 xc2s300e, 600e - i/o, l52p i/o i/o, l73n i/o, l73n_y i/o, l73n i/o, l73n_y i/o, l#p 4 aa13 xc2s300e, 600e - - - i/o, l73p i/o, l73p_y i/o, l73p i/o, l73p_y i/o 4 y13 - - - - - i/o i/o i/o i/o, l#n 4 w13 XC2S200E, 300e, 400e, 600e - i/o, l51n i/o, l68n i/o, l72n_y i/o, l72n_y i/o, l72n_y i/o, l72n_y i/o, vref bank 4, l#p 4 v13 XC2S200E, 300e, 400e, 600e all i/o, vref bank 4, l51p i/o, vref bank 4, l68p i/o, vref bank 4, l72p_y i/o, vref bank 4, l72p_y i/o, vref bank 4, l72p_y i/o, vref bank 4, l72p_y i/o 4 u13 - - i/o, l50n i/o, l67n i/o i/o i/o i/o i/o, l#n 4 ab14 - - i/o, l50p i/o, l67p i/o, l71n i/o, l71n i/o, l71n i/o, l71n i/o, l#p 4 aa14 - - - - i/o, l71p i/o, l71p i/o, l71p i/o, l71p i/o 4 ab15 - - - - i/o i/o i/o i/o i/o, l#n 4 y14 xc2s100e, 150e, 200e - i/o, l49n_y i/o, l66n_y i/o, l70n_y i/o, l70n i/o, l70n i/o, l70n i/o, l#p 4 w14 xc2s100e, 150e, 200e - i/o, l49p_y i/o, l66p_y i/o, l70p_y i/o, l70p i/o, l70p i/o, l70p i/o, l#n 4 u14 xc2s150e, 200e - - i/o, l65n_y i/o, l69n_y i/o, l69n i/o, l69n i/o, l69n i/o, l#p 4 v14 xc2s150e, 200e - - i/o, l65p_y i/o, l69p_y i/o, l69p i/o, l69p i/o, l69p i/o, l#n 4 aa15 xc2s100e, 200e, 300e, 400e, 600e - i/o, l48n_y i/o, l64n i/o, l68n_y i/o, l68n_y i/o, l68n_y i/o, l68n_y i/o, l#p 4 y15 xc2s100e, 200e, 300e, 400e, 600e - i/o, l48p_y i/o, l64p i/o, l68p_y i/o, l68p_y i/o, l68p_y i/o, l68p_y i/o, l#n 4 w15 xc2s100e, 200e, 300e, 400e, 600e - i/o, l47n_y i/o, l63n i/o, l67n_y i/o, l67n_y i/o, l67n_y i/o, l67n_y i/o, vref bank 4, l#p 4 v15 xc2s100e, 200e, 300e, 400e, 600e all i/o, vref bank 4, l47p_y i/o, vref bank 4, l63p i/o, vref bank 4, l67p_y i/o, vref bank 4, l67p_y i/o, vref bank 4, l67p_y i/o, vref bank 4, l67p_y i/o 4 ab16 - - - - - i/o i/o i/o i/o 4 ab17 - - i/o i/o i/o i/o i/o i/o fg456 pinouts (xc2s100e, xc2s150e, xc2s 200e, xc2s300e, xc 2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 25 r i/o, l#n 4 aa16 xc2s150e, 200e, 400e xc2s600e i/o, l46n i/o, l62n_y i/o, l66n_y i/o, l66n i/o, l66n_y i/o, vref bank 4, l66n i/o, l#p 4 y16 xc2s150e, 200e, 400e - i/o, l46p i/o, l62p_y i/o, l66p_y i/o, l66p i/o, l66p_y i/o, l66p i/o, l#n 4 w16 xc2s150e, 200e - - i/o, l61n_y i/o, l65n_y i/o, l65n i/o, l65n i/o, l65n i/o, l#p 4 v16 xc2s150e, 200e - - i/o, l61p_y i/o, l65p_y i/o, l65p i/o, l65p i/o, l65p i/o, l#n_yy 4 aa17 all - i/o, l45n_yy i/o, l60n_yy i/o, l64n_yy i/o, l64n_yy i/o, l64n_yy i/o, l64n_yy i/o, vref bank 4, l#p_yy 4 y17 all all i/o, vref bank 4, l45p_yy i/o, vref bank 4, l60p_yy i/o, vref bank 4, l64p_yy i/o, vref bank 4, l64p_yy i/o, vref bank 4, l64p_yy i/o, vref bank 4, l64p_yy i/o 4 ab18 xc2s100e - i/o, l44n_y i/o i/o i/o i/o i/o i/o, l#n 4 w17 xc2s100e, 400e, 600e - i/o, l44p_y i/o, l59n i/o, l63n i/o, l63n i/o, l63n_y i/o, l63n_y i/o, l#p 4 v17 xc2s400e, 600e - - i/o, l59p i/o, l63p i/o, l63p i/o, l63p_y i/o, l63p_y i/o 4 aa18 - - - - - i/o i/o i/o i/o, l#n 4 y18 xc2s100e, 200e, 300e, 400e, 600e - i/o, l43n_y i/o, l58n i/o, l62n_y i/o, l62n_y i/o, l62n_y i/o, l62n_y i/o, l#p 4 w18 xc2s100e, 200e, 300e, 400e, 600e XC2S200E, 300e, 400e, 600e i/o, l43p_y i/o, l58p i/o, vref bank 4, l62p_y i/o, vref bank 4, l62p_y i/o, vref bank 4, l62p_y i/o, vref bank 4, l62p_y i/o 4 ab19 - - i/o i/o i/o i/o i/o i/o i/o, l#n 4 aa19 xc2s150e, 400e - - i/o, l57n_y i/o, l61n i/o, l61n i/o, l61n_y i/o, l61n i/o, l#p 4 y19 xc2s150e, 400e - - i/o, l57p_y i/o, l61p i/o, l61p i/o, l61p_y i/o, l61p i/o 4 ab21 - - - - - i/o i/o i/o i/o, l#n_yy 4 ab20 all - i/o, l42n_yy i/o, l56n_yy i/o, l60n_yy i/o, l60n_yy i/o, l60n_yy i/o, l60n_yy i/o, l#p_yy 4 aa20 all - i/o, l42p_yy i/o, l56p_yy i/o, l60p_yy i/o, l60p_yy i/o, l60p_yy i/o, l60p_yy done 3 w20 - - done done done done done done program - y21 - - program program program program program program i/o (init ), l#n_yy 3 w21 all - i/o (init ), l41n_yy i/o (init ), l55n_yy i/o (init ), l59n_yy i/o (init ), l59n_yy i/o (init ), l59n_yy i/o (init ), l59n_yy i/o (d7), l#p_yy 3 y22 all - i/o (d7), l41p_yy i/o (d7), l55p_yy i/o (d7), l59p_yy i/o (d7), l59p_yy i/o (d7), l59p_yy i/o (d7), l59p_yy i/o 3 w22 - - - - - i/o i/o i/o i/o 3 v21 - - - i/o i/o i/o i/o i/o fg456 pinouts (xc2s100e, xc 2s150e, xc2s 200e, xc2s300e, xc2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 26 1-800-255-7778 product specification r i/o, l#n 3 v19 xc2s150e, 200e, 300e, 400e - - i/o, l54n_y i/o, l58n_y i/o, l58n_y i/o, l58n_y i/o, l58n i/o, l#p 3 v20 xc2s150e, 200e, 300e, 400e - i/o i/o, l54p_y i/o, l58p_y i/o, l58p_y i/o, l58p_y i/o, l58p i/o, l#n 3 v22 xc2s100e, 200e, 300e, 600e XC2S200E, 300e, 400e, 600e i/o, l40n_y i/o, l53n i/o, vref bank 3, l57n_y i/o, vref bank 3, l57n_y i/o, vref bank 3, l57n i/o, vref bank 3, l57n_y i/o, l#p 3 u22 xc2s100e, 200e, 300e, 600e - i/o, l40p_y i/o, l53p i/o, l57p_y i/o, l57p_y i/o, l57p i/o, l57p_y i/o 3 u21 - - - - - i/o i/o i/o i/o 3 u20 - - - i/o i/o i/o i/o i/o i/o, l#n 3 u18 xc2s100e, 200e, 300e, 600e - i/o, l39n_y i/o, l52n i/o, l56n_y i/o, l56n_y i/o, l56n i/o, l56n_y i/o, l#p 3 u19 xc2s100e, 200e, 300e, 600e - i/o, l39p_y i/o, l52p i/o, l56p_y i/o, l56p_y i/o, l56p i/o, l56p_y i/o, vref bank 3, l#n 3 t21 xc2s150e, 200e, 300e, 400e, 600e all i/o, vref bank 3, l38n i/o, vref bank 3, l51n_y i/o, vref bank 3, l55n_y i/o, vref bank 3, l55n_y i/o, vref bank 3, l55n_y i/o, vref bank 3, l55n_y i/o, l#p 3 t22 xc2s150e, 200e, 300e, 400e, 600e - i/o, l38p i/o, l51p_y i/o, l55p_y i/o, l55p_y i/o, l55p_y i/o, l55p_y i/o 3 t20 - - - i/o i/o i/o i/o i/o i/o, l#n 3 t18 xc2s150e, 200e, 300e, 400e - - i/o, l50n_y i/o, l54n_y i/o, l54n_y i/o, l54n_y i/o, l54n i/o, l#p 3 t19 xc2s150e, 200e, 300e, 400e - i/o i/o, l50p_y i/o, l54p_y i/o, l54p_y i/o, l54p_y i/o, l54p i/o, l#n 3 r21 xc2s100e, 150e, 300e, 600e xc2s600e i/o, l37n_y i/o, l49n_y i/o, l53n i/o, l53n_y i/o, l53n i/o, vref bank 3, l53n_y i/o, l#p 3 r22 xc2s100e, 150e, 300e, 600e - i/o, l37p_y i/o, l49p_y i/o, l53p i/o, l53p_y i/o, l53p i/o, l53p_y i/o 3 r20 - - - - - i/o i/o i/o i/o, vref bank 3, l#n 3 r18 xc2s300e, 400e, 600e all i/o, vref bank 3, l36n i/o, vref bank 3, l48n i/o, vref bank 3, l52n i/o, vref bank 3, l52n_y i/o, vref bank 3, l52n_y i/o, vref bank 3, l52n_y i/o (d6), l#p 3 r19 xc2s300e, 400e, 600e - i/o (d6), l36p i/o (d6), l48p i/o (d6), l52p i/o (d6), l52p_y i/o (d6), l52p_y i/o (d6), l52p_y i/o (d5), l#n_yy 3 p22 all - i/o (d5), l35n_yy i/o (d5), l47n_yy i/o (d5), l51n_yy i/o (d5), l51n_yy i/o (d5) l51n_yy i/o (d5), l51n_yy i/o, l#p_yy 3 p21 all - i/o, l35p_yy i/o, l47p_yy i/o, l51p_yy i/o, l51p_yy i/o, l51p_yy i/o, l51p_yy fg456 pinouts (xc2s100e, xc2s150e, xc2s 200e, xc2s300e, xc 2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 27 r i/o 3 p20 - - - - i/o i/o i/o i/o i/o, l#n 3 p18 xc2s150e, 200e, 300e, 400e - - i/o, l46n_y i/o, l50n_y i/o, l50n_y i/o, l50n_y i/o, l50n i/o, l#p 3 p19 xc2s100e, 150e, 200e, 300e, 400e - i/o, l34n_y i/o, l46p_y i/o, l50p_y i/o, l50p_y i/o, l50p_y i/o, l50p i/o, l#n 3 n22 xc2s100e, 150e, 200e, 300e, 600e - i/o, l34p_y i/o, l45n_y i/o, l49n_y i/o, l49n_y i/o, l49n i/o, l49n_y i/o, l#p 3 n21 xc2s150e, 200e, 300e, 600e - - i/o, l45p_y i/o, l49p_y i/o, l49p_y i/o, l49p i/o, l49p_y i/o 3 p17 - - - - i/o i/o i/o i/o i/o, l#n 3 n19 xc2s100e, 150e, 200e, 300e, 600e (1) - i/o, l33n_yy i/o, l44n_yy i/o, l48n_yy i/o, l48n_yy i/o, l48n i/o, l48n_y i/o, l#p 3 n20 xc2s100e, 150e, 200e, 300e, 600e (1) - i/o, l33p_yy i/o, l44p_yy i/o, l48p_yy i/o, l48p_yy i/o, l48p i/o, l48p_y i/o, vref bank 3, l#n 3 n18 xc2s300e, 400e, 600e all i/o, vref bank 3, l32n i/o, vref bank 3, l43n i/o, vref bank 3, l47n i/o, vref bank 3, l47n_y i/o, vref bank 3, l47n_y i/o, vref bank 3, l47n_y i/o (d4), l#p 3 n17 xc2s300e, 400e, 600e - i/o (d4), l32p i/o (d4), l43p i/o (d4), l47p i/o (d4), l47p_y i/o (d4), l47p_y i/o (d4), l47p_y i/o 3 m22 - - - - - i/o i/o i/o i/o, l#n 3 m20 xc2s300e, 400e - - - i/o, l46n i/o, l46n_y i/o, l46n_y i/o, l46n i/o, l#p 3 m21 xc2s100e, 150e, 300e, 400e - i/o, l31n_y i/o, l42n_y i/o, l46p i/o, l46p_y i/o, l46p_y i/o, l46p i/o, l#n 3 m18 xc2s100e, 150e, 200e, 300e, 600e xc2s400e, 600e i/o, l31p_y i/o, l42p_y i/o, l45n_y i/o, l45n_y i/o, vref bank 3, l45n i/o, vref bank 3, l45n_y i/o, l#p 3 m19 XC2S200E, 300e, 600e - - i/o i/o, l45p_y i/o, l45p_y i/o, l45p i/o, l45p_y i/o 3 m17 - - - - - i/o i/o i/o i/o (trdy) 3 l22 - - i/o (trdy) i/o (trdy) i/o (trdy) i/o (trdy) i/o (trdy) i/o (trdy) i/o (irdy), l#n_yy 2 l21 all - i/o (irdy), l30n_yy i/o (irdy), l41n_yy i/o (irdy), l44n_yy i/o (irdy), l44n_yy i/o (irdy), l44n_yy i/o (irdy), l44n_yy i/o, l#p_yy 2 l20 all - i/o, l30p_yy i/o, l41p_yy i/o, l44p_yy i/o, l44p_yy i/o, l44p_yy i/o, l44p_yy i/o 2 l19 - - - - - i/o i/o i/o i/o, l#n 2 l18 XC2S200E, 300e, 600e - - i/o i/o, l43n_y i/o, l43n_y i/o, l43n i/o, l43n_y fg456 pinouts (xc2s100e, xc 2s150e, xc2s 200e, xc2s300e, xc2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 28 1-800-255-7778 product specification r i/o, l#p 2 l17 xc2s100e, 150e, 200e, 300e, 600e xc2s400e, 600e i/o, l29n_y i/o, l40n_y i/o, l43p_y i/o, l43p_y i/o, vref bank 2, l43p i/o, vref bank 2, l43p_y i/o, l#n 2 k22 xc2s100e, 150e, 300e, 400e - i/o, l29p_y i/o, l40p_y i/o, l42n i/o, l42n_y i/o, l42n_y i/o, l42n i/o, l#p 2 k21 xc2s300e, 400e - - - i/o, l42p i/o, l42p_y i/o, l42p_y i/o, l42p i/o 2 k20 - - - - - i/o i/o i/o i/o (d3) 2 k19 - - i/o (d3) i/o (d3), l39n i/o (d3) i/o (d3) i/o (d3) i/o (d3) i/o, vref bank 2, l#n 2 k18 xc2s100e, 200e, 400e all i/o, vref bank 2, l28n_y i/o, vref bank 2, l39p i/o, vref bank 2, l41n_y i/o, vref bank 2, l41n i/o, vref bank 2, l41n_y i/o, vref bank 2, l41n i/o, l#p 2 k17 xc2s100, 150e, 200e, 400e - i/o, l28p_y i/o, l38n_y i/o, l41p_y i/o, l41p i/o, l41p_y i/o, l41p i/o, l#n 2 j22 xc2s150e, 300e, 600e - i/o i/o, l38p_y i/o, l40n i/o, l40n_y i/o, l40n i/o, l40n_y i/o, l#p 2 j21 xc2s300e, 600e - - - i/o, l40p i/o, l40p_y i/o, l40p i/o, l40p_y i/o, l#n 2 j20 xc2s150e, 200e, 300e, 600e - - i/o, l37n_y i/o, l39n_y i/o, l39n_y i/o, l39n i/o, l39n_y i/o, l#p 2 j19 xc2s100e, 150e, 200e, 300e, 600e - i/o, l27n_y i/o, l37p_y i/o, l39p_y i/o, l39p_y i/o, l39p i/o, l39p_y i/o 2 h22 xc2s100e, 150e - i/o, l27p_y i/o, l36n_y i/o i/o i/o i/o i/o, l#n 2 j18 xc2s150e, 200e, 300e, 400e, 600e - - i/o, l36p_y i/o, l38n_y i/o, l38n_y i/o, l38n_y i/o, l38n_y i/o, l#p 2 j17 XC2S200E, 300e, 400e, 600e - - - i/o, l38p_y i/o, l38p_y i/o, l38p_y i/o, l38p_y i/o, l#n 2 h21 xc2s150e, 200e, 300e, 400e, 600e - i/o i/o, l35n_y i/o, l37n_y i/o, l37n_y i/o, l37n_y i/o, l37n_y i/o (d2), l#p 2 h20 xc2s150e, 200e, 300e, 400e, 600e - i/o (d2) i/o (d2), l35p_y i/o (d2), l37p_y i/o (d2), l37p_y i/o (d2), l37p_y i/o (d2), l37p_y i/o (d1), l#n 2 h19 xc2s300e, 400e, 600e - i/o (d1), l26n i/o (d1), l34n i/o (d1), l36n i/o (d1), l36n_y i/o (d1), l36n_y i/o (d1), l36n_y i/o, vref bank 2, l#p 2 h18 xc2s300e, 400e, 600e all i/o, vref bank 2, l26p i/o, vref bank 2, l34p i/o, vref bank 2, l36p i/o, vref bank 2, l36p_y i/o, vref bank 2, l36p_y i/o, vref bank 2, l36p_y i/o 2 g22 - - - - - i/o i/o i/o i/o 2 f22 - - i/o i/o i/o i/o i/o i/o fg456 pinouts (xc2s100e, xc2s150e, xc2s 200e, xc2s300e, xc 2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 29 r i/o, l#n 2 g21 XC2S200E, 400e, 600e xc2s600e i/o, l25n i/o, l33n i/o, l35n_y i/o, l35n i/o, l35n_y i/o, vref bank 2, l35n_y i/o, l#p 2 g20 XC2S200E, 400e, 600e - i/o, l25p i/o, l33p i/o, l35p_y i/o, l35p i/o, l35p_y i/o, l35p_y i/o, l#n 2 g19 xc2s150e, 300e - - i/o, l32n_y i/o, l34n i/o, l34n_y i/o, l34n i/o, l34n i/o, l#p 2 g18 xc2s150e, 300e - - i/o, l32p_y i/o, l34p i/o, l34p_y i/o, l34p i/o, l34p i/o, l#n 2 e22 xc2s150e, 200e, 300e, 400e, 600e - i/o, l24n i/o, l31n_y i/o, l33n_y i/o, l33n_y i/o, l33n_y i/o, l33n_y i/o, vref bank 2, l#p 2 f21 xc2s150e, 200e, 300e, 400e, 600e all i/o, vref bank 2, l24p i/o, vref bank 2, l31p_y i/o, vref bank 2, l33p_y i/o, vref bank 2, l33p_y i/o, vref bank 2, l33p_y i/o, vref bank 2, l33p_y i/o 2 e21 xc2s100e - i/o, l23n_y i/o i/o i/o i/o i/o i/o, l#n 2 f20 xc2s100e, 150e, 200e, 300e, 400e, 600e - i/o, l23p_y i/o, l30n_y i/o, l32n_y i/o, l32n_y i/o, l32n_y i/o, l32n_y i/o, l#p 2 f19 xc2s150e, 200e, 300e, 400e, 600e - - i/o, l30p_y i/o, l32p_y i/o, l32p_y i/o, l32p_y i/o, l32p_y i/o 2 f18 - - - - - i/o i/o i/o i/o, l#n 2 d22 xc2s100e, 200e, 300e, 600e - i/o, l22n_y i/o, l29n i/o, l31n_y i/o, l31n_y i/o, l31n i/o, l31n_y i/o, l#p 2 d21 xc2s100e, 200e, 300e, 600e XC2S200E, 300e, 400e, 600e i/o, l22p_y i/o, l29p i/o, vref bank 2, l31p_y i/o, vref bank 2, l31p_y i/o, vref bank 2, l31p i/o, vref bank 2, l31p_y i/o, l#n 2 e20 XC2S200E, 300e, 400e - i/o i/o, l28n i/o, l30n_y i/o, l30n_y i/o, l30n_y i/o, l30n i/o, l#p 2 e19 XC2S200E, 300e, 400e - - i/o, l28p i/o, l30p_y i/o, l30p_y i/o, l30p_y i/o, l30p i/o 2 d20 - - - - - i/o i/o i/o i/o (din, d0), l#n_yy 2 c22 all - i/o (din, d0), l21n_yy i/o (din, d0), l27n_yy i/o (din, d0), l29n_yy i/o (din, d0), l29n_yy i/o (din, d0), l29n_yy i/o (din, d0), l29n_yy i/o (dout, busy), l#p_yy 2 c21 all - i/o (dout, busy), l21p_yy i/o (dout, busy), l27p_yy i/o (dout, busy), l29p_yy i/o (dout, busy), l29p_yy i/o (dout, busy), l29p_yy i/o (dout, busy), l29p_yy cclk 2 b22 - - cclk cclk cclk cclk cclk cclk tdo 2 a21 - - tdo tdo tdo tdo tdo tdo tdi - c19 - - tdi tdi tdi tdi tdi tdi i/o (cs ), l#p_yy 1 b20 all - i/o (cs ), l20p_yy i/o (cs ), l26p_yy i/o (cs ), l28p_yy i/o (cs ), l28p_yy i/o (cs ), l28p_yy i/o (cs ), l28p_yy fg456 pinouts (xc2s100e, xc 2s150e, xc2s 200e, xc2s300e, xc2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 30 1-800-255-7778 product specification r i/o (write ), l#n_yy 1 a20 all - i/o (write ), l20n_yy i/o (write ), l26n_yy i/o (write ), l28n_yy i/o (write ), l28n_yy i/o (write ), l28n_yy i/o (write ), l28n_yy i/o 1 d18 - - - - - i/o i/o i/o i/o 1 c18 - - - i/o i/o i/o i/o i/o i/o, l#p 1 b19 XC2S200E, 300e, 400e, 600e - - i/o, l25p i/o, l27p_y i/o, l27p_y i/o, l27p_y i/o, l27p_y i/o, l#n 1 a19 XC2S200E, 300e, 400e, 600e - i/o i/o, l25n i/o, l27n_y i/o, l27n_y i/o, l27n_y i/o, l27n_y i/o, l#p 1 b18 xc2s100e, 200e, 300e, 400e, 600e XC2S200E, 300e, 400e, 600e i/o, l19p_y i/o, l24p i/o, vref bank 1, l26p_y i/o, vref bank 1, l26p_y i/o, vref bank 1, l26p_y i/o, vref bank 1, l26p_y i/o, l#n 1 a18 xc2s100e, 200e, 300e, 400e, 600e - i/o, l19n_y i/o, l24n i/o, l26n_y i/o, l26n_y i/o, l26n_y i/o, l26n_y i/o 1 d17 - - - - - i/o i/o i/o i/o 1 c17 - - - i/o i/o i/o i/o i/o i/o, l#p_yy 1 b17 all - i/o, l18p_yy i/o, l23p_yy i/o, l25p_yy i/o, l25p_yy i/o, l25p_yy i/o, l25p_yy i/o, l#n_yy 1 a17 all - i/o, l18n_yy i/o, l23n_yy i/o, l25n_yy i/o, l25n_yy i/o, l25n_yy i/o, l25n_yy i/o, vref bank 1, l#p_yy 1 e16 all all i/o, vref bank 1, l17p_yy i/o, vref bank 1, l22p_yy i/o, vref bank 1, l24p_yy i/o, vref bank 1, l24p_yy i/o, vref bank 1, l24p_yy i/o, vref bank 1, l24p_yy i/o, l#n_yy 1 e17 all - i/o, l17n_yy i/o, l22n_yy i/o, l24n_yy i/o, l24n_yy i/o, l24n_yy i/o, l24n_yy i/o 1 e15 - - - i/o i/o i/o i/o i/o i/o, l#p 1 d16 xc2s300e, 600e - - i/o, l21p i/o, l23p i/o, l23p_y i/o, l23p i/o, l23p_y i/o, l#n 1 c16 xc2s300e, 600e - i/o i/o, l21n i/o, l23n i/o, l23n_y i/o, l23n i/o, l23n_y i/o, l#p 1 b16 xc2s100e, 300e, 600e xc2s600e i/o, l16p_y i/o, l20p i/o, l22p i/o, l22p_y i/o, l22p i/o, vref bank 1, l22p_y i/o, l#n 1 a16 xc2s100e, 300e, 600e - i/o, l16n_y i/o, l20n i/o, l22n i/o, l22n_y i/o, l22n i/o, l22n_y i/o 1 f14 - - - - - i/o i/o i/o i/o, vref bank 1, l#p 1 d15 xc2s100e, 200e, 300e, 400e, 600e all i/o, vref bank 1, l15p_y i/o, vref bank 1, l19p i/o, vref bank 1, l21p_y i/o, vref bank 1, l21p_y i/o, vref bank 1, l21p_y i/o, vref bank 1, l21p_y i/o, l#n 1 c15 xc2s100e, 200e, 300e, 400e, 600e - i/o, l15n_y i/o, l19n i/o, l21n_y i/o, l21n_y i/o, l21n_y i/o, l21n_y i/o, l#p 1 b15 xc2s100e, 200e, 300e, 400e, 600e - i/o, l14p_y i/o, l18p i/o, l20p_y i/o, l20p_y i/o, l20p_y i/o, l20p_y fg456 pinouts (xc2s100e, xc2s150e, xc2s 200e, xc2s300e, xc 2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 31 r i/o, l#n 1 a15 xc2s100e, 200e, 300e, 400e, 600e - i/o, l14n_y i/o, l18n i/o, l20n_y i/o, l20n_y i/o, l20n_y i/o, l20n_y i/o 1 e14 - - - - i/o i/o i/o i/o i/o, l#p 1 d14 xc2s150e, 300e, 400e, 600e - - i/o, l17p_y i/o, l19p i/o, l19p_y i/o, l19p_y i/o, l19p_y i/o, l#n 1 c14 xc2s100e, 150e, 300e, 400e, 600e - i/o, l13p_y i/o, l17n_y i/o, l19n i/o, l19n_y i/o, l19n_y i/o, l19n_y i/o, l#p 1 b14 xc2s100e, 150e, 300e, 400e, 600e - i/o, l13n_y i/o, l16p_y i/o, l18p i/o, l18p_y i/o, l18p_y i/o, l18p_y i/o, l#n 1 a14 xc2s150e, 300e, 400e, 600e - - i/o, l16n_y i/o, l18n i/o, l18n_y i/o, l18n_y i/o, l18n_y i/o 1 e13 - - - - i/o i/o i/o i/o i/o, l#p 1 d13 XC2S200E, 300e, 400e, 600e - i/o, l12p i/o, l15p i/o, l17p_y i/o, l17p_y i/o, l17p_y i/o, l17p_y i/o, l#n 1 c13 XC2S200E, 300e, 400e, 600e - i/o, l12n i/o, l15n i/o, l17n_y i/o, l17n_y i/o, l17n_y i/o, l17n_y i/o, vref bank 1, l#p 1 b13 XC2S200E, 300e, 400e, 600e all i/o, vref bank 1, l11p i/o, vref bank 1, l14p i/o, vref bank 1, l16p_y i/o, vref bank 1, l16p_y i/o, vref bank 1, l16p_y i/o, vref bank 1, l16p_y i/o, l#n 1 a13 XC2S200E, 300e, 400e, 600e - i/o, l11n i/o, l14n i/o, l16n_y i/o, l16n_y i/o, l16n_y i/o, l16n_y i/o 1 f13 - - - - - i/o i/o i/o i/o, l#p 1 c12 xc2s300e, 600e - - - i/o, l15p i/o, l15p_y i/o, l15p i/o, l15p_y i/o, l#n 1 b12 xc2s300e, 600e - i/o, l10p i/o i/o, l15n i/o, l15n_y i/o, l15n i/o, l15n_y i/o, l#p 1 d12 xc2s150e, 300e, 600e xc2s400e, 600e i/o, l10n i/o, l13p_y i/o, l14p i/o, l14p_y i/o, vref bank 1, l14p i/o, vref bank 1, l14p_y i/o, l#n 1 e12 xc2s150e, 300e, 600e - - i/o, l13n_y i/o, l14n i/o, l14n_y i/o, l14n i/o, l14n_y i/o 1 f12 - - - - - i/o i/o i/o i/o (dll), l#p 1 a12 - - i/o (dll), l9p i/o (dll), l12p i/o (dll), l13p i/o (dll), l13p i/o (dll), l13p i/o (dll), l13p gck2, i 1 a11 - - gck2, i gck2, i gck2, i gck2, i gck2, i gck2, i gck3, i 0 c11 - - gck3, i gck3, i gck3, i gck3, i gck3, i gck3, i i/o (dll), l#n 0 b11 - - i/o (dll), l9n i/o (dll), l12n i/o (dll), l13n i/o (dll), l13n i/o (dll), l13n i/o (dll), l13n i/o 0 d11 - - - - - i/o i/o i/o fg456 pinouts (xc2s100e, xc 2s150e, xc2s 200e, xc2s300e, xc2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 32 1-800-255-7778 product specification r i/o 0 f11 - xc2s400e, 600e - - i/o i/o i/o, vref bank 0 i/o, vref bank 0 i/o, l#p 0 a10 xc2s300e, 600e - i/o i/o, l11p i/o, l12p i/o, l12p_y i/o, l12p i/o, l12p_y i/o, l#n 0 b10 xc2s300e, 600e - - i/o, l11n i/o, l12n i/o, l12n_y i/o, l12n i/o, l12n_y i/o 0 e11 - - - - - i/o i/o i/o i/o, l#p 0 c10 XC2S200E, 300e, 400e, 600e - i/o, l8p i/o, l10p i/o, l11p_y i/o, l11p_y i/o, l11p_y i/o, l11p_y i/o, vref bank 0, l#n 0 d10 XC2S200E, 300e, 400e, 600e all i/o, vref bank 0, l8n i/o, vref bank 0, l10n i/o, vref bank 0, l11n_y i/o, vref bank 0, l11n_y i/o, vref bank 0, l11n_y i/o, vref bank 0, l11n_y i/o 0 f10 - - i/o, l7p i/o i/o i/o i/o i/o i/o, l#p 0 a9 - - i/o, l7n i/o i/o, l10p i/o, l10p i/o, l10p i/o, l10p i/o, l#n 0 b9 - - - - i/o, l10n i/o, l10n i/o, l10n i/o, l10n i/o 0 e10 - - - - i/o i/o i/o i/o i/o, l#p 0 c9 xc2s100e, 150e, 200e - i/o, l6p_y i/o, l9p_y i/o, l9p_y i/o, l9p i/o, l9p i/o, l9p i/o, l#n 0 d9 xc2s100e, 150e, 200e - i/o, l6n_y i/o, l9n_y i/o, l9n_y i/o, l9n i/o, l9n i/o, l9n i/o, l#p 0 f9 xc2s150e, 200e - - i/o, l8p_y i/o, l8p_y i/o, l8p i/o, l8p i/o, l8p i/o, l#n 0 e9 xc2s150e, 200e - - i/o, l8n_y i/o, l8n_y i/o, l8n i/o, l8n i/o, l8n i/o, l#p 0 a8 xc2s100e, 200e, 300e, 400e, 600e - i/o, l5p_y i/o, l7p i/o, l7p_y i/o, l7p_y i/o, l7p_y i/o, l7p_y i/o, l#n 0 b8 xc2s100e, 200e, 300e, 400e, 600e - i/o, l5n_y i/o, l7n i/o, l7n_y i/o, l7n_y i/o, l7n_y i/o, l7n_y i/o, l#p 0 c8 xc2s100e, 200e, 300e, 400e, 600e - i/o, l4p_y i/o, l6p i/o, l6p_y i/o, l6p_y i/o, l6p_y i/o, l6p_y i/o, vref bank 0, l#n 0 d8 xc2s100e, 200e, 300e, 400e, 600e all i/o, vref bank 0, l4n_y i/o, vref bank 0, l6n i/o, vref bank 0, l6n_y i/o, vref bank 0, l6n_y i/o, vref bank 0, l6n_y i/o, vref bank 0, l6n_y i/o 0 a7 - - - - - i/o i/o i/o i/o 0 b7 - - i/o i/o i/o i/o i/o i/o i/o, l#p 0 c7 xc2s150e, 200e xc2s600e i/o, l3p i/o, l5p_y i/o, l5p_y i/o, l5p i/o, l5p i/o, vref bank 0, l5p i/o, l#n 0 d7 xc2s150e, 200e - i/o, l3n i/o, l5n_y i/o, l5n_y i/o, l5n i/o, l5n i/o, l5n i/o, l#p 0 e8 xc2s150e, 200e - - i/o, l4p_y i/o, l4p_y i/o, l4p i/o, l4p i/o, l4p i/o, l#n 0 e7 xc2s150e, 200e - - i/o, l4n_y i/o, l4n_y i/o, l4n i/o, l4n i/o, l4n fg456 pinouts (xc2s100e, xc2s150e, xc2s 200e, xc2s300e, xc 2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 33 r i/o, l#p_yy 0 a6 all - i/o, l2p_yy i/o, l3p_yy i/o, l3p_yy i/o, l3p_yy i/o, l3p_yy i/o, l3p_yy i/o, vref bank 0, l#n_yy 0 b6 all all i/o, vref bank 0, l2n_yy i/o, vref bank 0, l3n_yy i/o, vref bank 0, l3n_yy i/o, vref bank 0, l3n_yy i/o, vref bank 0, l3n_yy i/o, vref bank 0, l3n_yy i/o 0 c6 xc2s100e - i/o, l1p_y i/o i/o i/o i/o i/o i/o, l#p 0 a5 xc2s100e - i/o, l1n_y i/o, l2p i/o, l2p i/o, l2p i/o, l2p i/o, l2p i/o, l#n 0 b5 - - - i/o, l2n i/o, l2n i/o, l2n i/o, l2n i/o, l2n i/o 0 d6 - - - - - i/o i/o i/o i/o, l#p 0 b4 xc2s100e, 200e, 300e, 400e, 600e - i/o, l0p_y i/o, l1p i/o, l1p_y i/o, l1p_y i/o, l1p_y i/o, l1p_y i/o, l#n 0 c5 xc2s100e, 200e, 300e, 400e, 600e XC2S200E, 300e, 400e, 600e i/o, l0n_y i/o, l1n i/o, vref bank 0, l1n_y i/o, vref bank 0, l1n_y i/o, vref bank 0, l1n_y i/o, vref bank 0, l1n_y i/o 0 a4 - - i/o i/o i/o i/o i/o i/o i/o, l#p 0 a3 xc2s150e, 400e, 600e - - i/o, l0p_y i/o, l0p i/o, l0p i/o, l0p_y i/o, l0p_y i/o, l#n 0 b3 xc2s150e, 400e, 600e - - i/o, l0n_y i/o, l0n i/o, l0n i/o, l0n_y i/o, l0n_y i/o 0 c4 - - - - - i/o i/o i/o i/o 0 d5 - - i/o i/o i/o i/o i/o i/o tck - e6 - - tck tck tck tck tck tck notes: 1. although designated with the _yy suffix in the xc2s100e, xc2s15 0e, XC2S200E, and xc2s300e, these differential pairs are not asynchronous in the xc2s400e. fg456 pinouts (xc2s100e, xc 2s150e, xc2s 200e, xc2s300e, xc2s400e, xc2s600e) pad name pin lv d s async. output option v ref option device-specific pinouts: xc2s function bank 100e 150e 200e 300e 400e 600e fg456 differential clock pins clock bank p n pin name pin name gck0 4 aa12 gck0, i y12 i/o (dll), l#p gck1 5 ab12 gck1, i ab11 i/o (dll), l#n gck2 1 a11 gck2, i a12 i/o (dll), l#p gck3 0 c11 gck3, i b11 i/o (dll), l#n additional fg456 package pins vccint pins d4 (1) d19 (1) e5 e18 f6 f17 g7 g8 g15 g16 h7 h16 r7 r16 t7 t8 t15 t16 u6 u17 v5 v18 w4 (1) w19 (1) - - - vcco bank 0 pins f7 f8 g9 g10 - - - - - vcco bank 1 pins
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 34 1-800-255-7778 product specification r f15 f16 g13 g14 - - - - - vcco bank 2 pins g17 h17 j16 k16 - - - - - vcco bank 3 pins n16 p16 r17 t17 - - - - - vcco bank 4 pins t13 t14 u15 u16 - - - - - vcco bank 5 pins t9 t10 u7 u8 - - - - - vcco bank 6 pins n7 p7 r6 t6 - - - - - vcco bank 7 pins g6 h6 j7 k7 - - - - - gnd pins a1 a2 (2) a22 b1 (2) b2 b21 c3 c20 g11 g12 j9 j10 j11 j12 j13 j14 k9 k10 k11 k12 k13 k14 l7 l9 l10 l11 l12 l13 l14 l16 m7 m9 m10 m11 m12 m13 m14 m16 n9 n10 n11 n12 n13 n14 p9 p10 p11 p12 p13 p14 t11 t12 y20 y3 y4 (2) aa2 aa4 (2) aa21 aa22 (2) ab1 ab22 - - not connected pins a2 (2) b1 (2) d4 (1) d19 (1) w4 (1) w19 (1) y4 (2) aa4 (2) aa22 (2) notes: 1. vccint connections in xc2s400e and xc2s600e. no connects (no internal connection) in xc2s100e, xc2s150e, XC2S200E, and xc2s300e. 2. gnd connections in xc2s400e and xc2s600e. no connects (n o internal connection) in xc2s100e, xc2s150e, XC2S200E, and xc2s300e fg676 pinouts (xc2s400e, xc2s600e) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e tms - b1 - - tms tms i/o 7 d3 - - i/o i/o i/o, l204p 7 c2 - - - i/o, l204p i/o, l204n 7 c1 - - - i/o, l204n i/o, l203p 7 d2 xc2s600e - - i/o, l203p_y i/o, l203n 7 d1 xc2s600e - i/o i/o, l203n_y i/o, l202p_yy 7 e2 all - i/o, l202p_yy i/o, l202p_yy i/o, l202n_yy 7 e1 all - i/o, l202n_yy i/o, l202n_yy i/o, l201p 7 e4 xc2s400e - i/o, l201p_y i/o, l201p additional fg456 package pins (continued)
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 35 r i/o, l201n 7 f5 xc2s400e - i/o, l201n_y i/o, l201n i/o, vref bank 7, l200p 7 f4 xc2s600e all i/o, vref bank 7, l200p i/o, vref bank 7, l200p_y i/o, l200n 7 f3 xc2s600e - i/o, l200n i/o, l200n_y i/o, l199p 7 f2 xc2s600e - - i/o, l199p_y i/o, l199n 7 f1 xc2s600e - i/o i/o, l199n_y i/o, l198p 7 g6 xc2s400e - i/o, l198p_y i/o, l198p i/o, l198n 7 g5 xc2s400e - i/o, l198n_y i/o, l198n i/o, l197p 7 g4 xc2s600e - i/o, l197p i/o, l197p_y i/o, l197n 7 g3 xc2s600e - i/o, l197n i/o, l197n_y i/o, vref bank 7, l196p_yy 7 g2 all all i/o, vref bank 7, l196p_yy i/o, vref bank 7, l196p_yy i/o, l196n_yy 7 g1 all - i/o, l196n_yy i/o, l196n_yy i/o 7 h7 - - i/o i/o i/o, l195p_yy 7 h6 all - i/o, l195p_yy i/o, l195p_yy i/o, l195n_yy 7 h5 all - i/o, l195n_yy i/o, l195n_yy i/o 7 j8 - - - i/o i/o, l194p 7 h2 xc2s400e - i/o, l194p_y i/o, l194p i/o, l194n 7 h1 xc2s400e - i/o, l194n_y i/o, l194n i/o, l193p 7 j7 xc2s600e xc2s600e i/o i/o, vref bank 7, l193p_y i/o, l193n 7 j6 xc2s600e - - i/o, l193n_y i/o 7 j5 - - i/o i/o i/o, l192p_yy 7 j4 all - i/o, l192p_yy i/o, l192p_yy i/o, l192n_yy 7 j3 all - i/o, l192n_yy i/o, l192n_yy i/o 7 k5 - - i/o i/o i/o, vref bank 7, l191p_yy 7 j2 all all i/o, vref bank 7, l191p_yy i/o, vref bank 7, l191p_yy i/o, l191n_yy 7 j1 all - i/o, l191n_yy i/o, l191n_yy i/o, l190p_yy 7 k8 all - i/o, l190p_yy i/o, l190p_yy i/o, l190n_yy 7 k7 all - i/o, l190n_yy i/o, l190n_yy i/o 7 k4 - - - i/o i/o, l189p_yy 7 k3 all - i/o, l189p_yy i/o, l189p_yy i/o, l189n_yy 7 k2 all - i/o, l189n_yy i/o, l189n_yy i/o 7 k1 - - - i/o i/o, l188p 7 l8 xc2s400e - i/o, l188p_y i/o, l188p fg676 pinouts (xc2s4 00e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 36 1-800-255-7778 product specification r i/o, l188n 7 l7 xc2s400e - i/o, l188n_y i/o, l188n i/o, l187p 7 l6 xc2s600e - i/o, l187p i/o, l187p_y i/o, l187n 7 l5 xc2s600e - i/o, l187n i/o, l187n_y i/o 7 l3 - - - i/o i/o, l186p 7 l2 xc2s600e - i/o, l186p i/o, l186p_y i/o, l186n 7 l1 xc2s600e - i/o, l186n i/o, l186n_y i/o 7 m9 - - - i/o i/o, l185p 7 m8 xc2s600e - i/o, l185p i/o, l185p_y i/o, l185n 7 m7 xc2s600e - i/o, l185n i/o, l185n_y i/o, vref bank 7, l184p_yy 7 m6 all all i/o, vref bank 7, l184p_yy i/o, vref bank 7, l184p_yy i/o, l184n_yy 7 m5 all - i/o, l184n_yy i/o, l184n_yy i/o 7 m4 - - - i/o i/o, l183p_yy 7 m2 all - i/o, l183p_yy i/o, l183p_yy i/o, l183n_yy 7 m1 all - i/o, l183n_yy i/o, l183n_yy i/o 7 n9 - - - i/o i/o, l182p 7 n8 xc2s400e - i/o, l182p_y i/o, l182p i/o, l182n 7 n7 xc2s400e - i/o, l182n_y i/o, l182n i/o, vref bank 7, l181p 7 n6 xc2s600e all i/o, vref bank 7, l181p i/o, vref bank 7, l181p_y i/o, l181n 7 n5 xc2s600e - i/o, l181n i/o, l181n_y i/o 7 n4 - - - i/o i/o, l180p_yy 7 n3 all - i/o, l180p_yy i/o, l180p_yy i/o, l180n_yy 7 n2 all - i/o, l180n_yy i/o, l180n_yy i/o 7 n1 - - - i/o i/o, l179p_yy 7 p1 all - i/o, l179p_yy i/o, l179p_yy i/o (irdy), l179n_yy 7 p2 all - i/o (irdy), l179n_yy i/o (irdy), l179n_yy i/o (trdy), l178p 6 p3 xc2s600e - i/o (trdy) i/o (trdy), l178p_y i/o, l178n 6 p4 xc2s600e - - i/o, l178n_y i/o, l177p 6 p5 xc2s600e - - i/o, l177p_y i/o, l177n 6 p6 xc2s600e - i/o i/o, l177n_y i/o 6 p7 - - i/o i/o i/o, l176p 6 p8 xc2s600e - i/o, l176p i/o, l176p_y fg676 pinouts (xc2s400e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 37 r i/o, vref bank 6, l176n 6 p9 xc2s600e all i/o, vref bank 6, l176n i/o, vref bank 6, l176n_y i/o, l175p 6 r1 xc2s400e - i/o, l175p_y i/o, l175p i/o, l175n 6 r2 xc2s400e - i/o, l175n_y i/o, l175n i/o 6 r4 - - - i/o i/o, l174p_yy 6 r5 all - i/o, l174p_yy i/o, l174p_yy i/o, l174n_yy 6 r6 all - i/o, l174n_yy i/o, l174n_yy i/o 6 r7 - - - i/o i/o, l173p_yy 6 r8 all - i/o, l173p_yy i/o, l173p_yy i/o, vref bank 6, l173n_yy 6 r9 all all i/o, vref bank 6, l173n_yy i/o, vref bank 6, l173n_yy i/o, l172p 6 t1 xc2s600e - i/o, l172p i/o, l172p_y i/o, l172n 6 t2 xc2s600e - i/o, l172n i/o, l172n_y i/o 6 t3 - - - i/o i/o, l171p 6 t5 xc2s600e - i/o, l171p i/o, l171p_y i/o, l171n 6 t6 xc2s600e - i/o, l171n i/o, l171n_y i/o 6 u1 - - - i/o i/o, l170p 6 t7 xc2s600e - i/o, l170p i/o, l170p_y i/o, l170n 6 t8 xc2s600e - i/o, l170n i/o, l170n_y i/o, l169p 6 u2 xc2s400e - i/o, l169p_y i/o, l169p i/o, l169n 6 u3 xc2s400e - i/o, l169n_y i/o, l169n i/o 6 u7 - - - i/o i/o, l168p 6 u4 xc2s600e - - i/o, l168p_y i/o, l168n 6 u5 xc2s600e - i/o i/o, l168n_y i/o 6 u8 - - i/o i/o i/o, l167p_yy 6 v1 all - i/o, l167p_yy i/o, l167p_yy i/o, l167n_yy 6 v2 all - i/o, l167n_yy i/o, l167n_yy i/o 6 v3 - - i/o i/o i/o, vref bank 6, l166p_yy 6 v4 all all i/o, vref bank 6, l166p_yy i/o, vref bank 6, l166p_yy i/o, l166n_yy 6 v5 all - i/o, l166n_yy i/o, l166n_yy i/o, l165p_yy 6 v6 all - i/o, l165p_yy i/o, l165p_yy i/o, l165n_yy 6 v7 all - i/o, l165n_yy i/o, l165n_yy i/o 6 v8 - - - i/o i/o, l164p 6 w1 xc2s600e - i/o, l164p i/o, l164p_y fg676 pinouts (xc2s4 00e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 38 1-800-255-7778 product specification r i/o, l164n 6 w2 xc2s600e xc2s600e i/o, l164n i/o, vref bank 6, l164n_y i/o, l163p 6 w5 xc2s400e - i/o, l163p_y i/o, l163p i/o, l163n 6 w6 xc2s400e - i/o, l163n_y i/o, l163n i/o 6 w7 - - i/o i/o i/o, l162p_yy 6 y1 all - i/o, l162p_yy i/o, l162p_yy i/o, l162n_yy 6 y2 all - i/o, l162n_yy i/o, l162n_yy i/o 6 y3 - - - i/o i/o, l161p_yy 6 y4 all - i/o, l161p_yy i/o, l161p_yy i/o, vref bank 6, l161n_yy 6 y5 all all i/o, vref bank 6, l161n_yy i/o, vref bank 6, l161n_yy i/o 6 y6 - - i/o i/o i/o, l160p_yy 6 aa1 all - i/o, l160p_yy i/o, l160p_yy i/o, l160n_yy 6 aa2 all - i/o, l160n_yy i/o, l160n_yy i/o, l159p 6 aa3 xc2s600e - i/o, l159p i/o, l159p_y i/o, l159n 6 aa4 xc2s600e - i/o, l159n i/o, l159n_y i/o 6 y7 - - - i/o i/o, l158p 6 aa5 xc2s600e - i/o, l158p i/o, l158p_y i/o, vref bank 6, l158n 6 ab5 xc2s600e all i/o, vref bank 6, l158n i/o, vref bank 6, l158n_y i/o, l157p 6 ab1 xc2s400e - i/o, l157p_y i/o, l157p i/o, l157n 6 ab2 xc2s400e - i/o, l157n_y i/o, l157n i/o, l156p 6 ac1 xc2s600e - - i/o, l156p_y i/o, l156n 6 ac2 xc2s600e - i/o i/o, l156n_y i/o, l155p_yy 6 ac3 all - i/o, l155p_yy i/o, l155p_yy i/o, l155n_yy 6 ab4 all - i/o, l155n_yy i/o, l155n_yy i/o, l154p 6 ad1 - - - i/o, l154p i/o, l154n 6 ad2 - - - i/o, l154n i/o, l153p_yy 6 ae1 all - i/o, l153p_yy i/o, l153p_yy i/o, l153n_yy 6 af2 all - i/o, l153n_yy i/o, l153n_yy m1 - ae3 - - m1 m1 m0 - af3 - - m0 m0 m2 - ad4 - - m2 m2 fg676 pinouts (xc2s400e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 39 r i/o 5 ac5 - - i/o i/o i/o, l152n 5 ae4 - - i/o i/o, l152n i/o, l152p 5 af4 - - - i/o, l152p i/o, l151n 5 ae5 - - - i/o, l151n i/o, l151p 5 af5 - - i/o i/o, l151p i/o, l150n 5 aa6 xc2s400e - i/o, l150n_y i/o, l150n i/o, l150p 5 ab6 xc2s400e - i/o, l150p_y i/o, l150p i/o, l149n_yy 5 ac6 all - i/o, l149n_yy i/o, l149n_yy i/o, l149p_yy 5 ad6 all - i/o, l149p_yy i/o, l149p_yy i/o, vref bank 5, l148n_yy 5 ae6 all all i/o, vref bank 5, l148n_yy i/o, vref bank 5, l148n_yy i/o, l148p_yy 5 af6 all - i/o, l148p_yy i/o, l148p_yy i/o, l147n 5 aa7 xc2s600e - - i/o, l147n_y i/o, l147p 5 ab7 xc2s600e - i/o i/o, l147p_y i/o, l146n_yy 5 ac7 all - i/o, l146n_yy i/o, l146n_yy i/o, l146p_yy 5 ad7 all - i/o, l146p_yy i/o, l146p_yy i/o, l145n_yy 5 ae7 all - i/o, l145n_yy i/o, l145n_yy i/o, l145p_yy 5 af7 all - i/o, l145p_yy i/o, l145p_yy i/o, vref bank 5, l144n_yy 5 y8 all all i/o, vref bank 5, l144n_yy i/o, vref bank 5, l144n_yy i/o, l144p_yy 5 aa8 all - i/o, l144p_yy i/o, l144p_yy i/o, l143n_yy 5 ae8 all - i/o, l143n_yy i/o, l143n_yy i/o, l143p_yy 5 af8 all - i/o, l143p_yy i/o, l143p_yy i/o 5 ab8 - - i/o i/o i/o, l142n 5 w9 xc2s600e - i/o, l142n i/o, l142n_y i/o, l142p 5 y9 xc2s600e - i/o, l142p i/o, l142p_y i/o, l141n 5 aa9 xc2s600e xc2s600e - i/o, vref bank 5, l141n_y i/o, l141p 5 ab9 xc2s600e - i/o i/o, l141p_y i/o, l140n_yy 5 ac9 all - i/o, l140n_yy i/o, l140n_yy i/o, l140p_yy 5 ad9 all - i/o, l140p_yy i/o, l140p_yy i/o, l139n_yy 5 ae9 all - i/o, l139n_yy i/o, l139n_yy i/o, l139p_yy 5 af9 all - i/o, l139p_yy i/o, l139p_yy i/o, vref bank 5, l138n_yy 5 w10 all all i/o, vref bank 5, l138n_yy i/o, vref bank 5, l138n_yy fg676 pinouts (xc2s4 00e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 40 1-800-255-7778 product specification r i/o, l138p_yy 5 y10 all - i/o, l138p_yy i/o, l138p_yy i/o, l137n_yy 5 ab10 all - i/o, l137n_yy i/o, l137n_yy i/o, l137p_yy 5 ac10 all - i/o, l137p_yy i/o, l137p_yy i/o 5 ad10 - - - i/o i/o, l136n 5 ae10 xc2s600e - i/o, l136n i/o, l136n_y i/o, l136p 5 af10 xc2s600e - i/o, l136p i/o, l136p_y i/o 5 ad11 - - - i/o i/o, l135n_yy 5 w11 all - i/o, l135n_yy i/o, l135n_yy i/o, l135p_yy 5 y11 all - i/o, l135p_yy i/o, l135p_yy i/o, l134n_yy 5 aa11 all - i/o, l134n_yy i/o, l134n_yy i/o, l134p_yy 5 ab11 all - i/o, l134p_yy i/o, l134p_yy i/o 5 v12 - - - i/o i/o, l133n 5 ae11 - - i/o, l133n i/o, l133n i/o, l133p 5 af11 - - i/o, l133p i/o, l133p i/o 5 w12 - - - i/o i/o, l132n_yy 5 y12 all - i/o, l132n_yy i/o, l132n_yy i/o, l132p_yy 5 aa12 all - i/o, l132p_yy i/o, l132p_yy i/o, vref bank 5, l131n_yy 5 ab12 all all i/o, vref bank 5, l131n_yy i/o, vref bank 5, l131n_yy i/o, l131p_yy 5 ac12 all - i/o, l131p_yy i/o, l131p_yy i/o 5 v13 - - - i/o i/o, l130n_yy 5 ae12 all - i/o, l130n_yy i/o, l130n_yy i/o, l130p_yy 5 af12 all - i/o, l130p_yy i/o, l130p_yy i/o 5 w13 - - - i/o i/o, l129n 5 y13 xc2s600e - i/o, l129n i/o, l129n_y i/o, l129p 5 aa13 xc2s600e - i/o, l129p i/o, l129p_y i/o, vref bank 5, l128n 5 ab13 xc2s600e all i/o, vref bank 5, l128n i/o, vref bank 5, l128n_y i/o, l128p 5 ac13 xc2s600e - i/o, l128p i/o, l128p_y i/o 5 ad13 - - - i/o i/o, l127n 5 v14 - - i/o i/o, l127n i/o, l127p 5 w14 - - - i/o, l127p i/o (dll), l126n 5 ae13 - - i/o (dll), l126n i/o (dll), l126n gck1, i 5 af13 - - gck1, i gck1, i fg676 pinouts (xc2s400e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 41 r gck0, i 4 af14 - - gck0, i gck0, i i/o (dll), l126p 4 ae14 - - i/o (dll), l126p i/o (dll), l126p i/o 4 ad14 - - - i/o i/o, l125n 4 ac14 - - i/o, l125n i/o, l125n i/o, l125p 4 ab14 - - i/o, l125p i/o, l125p i/o 4 ac15 - - - i/o i/o, l124n 4 aa14 xc2s600e - i/o, l124n i/o, l124n_y i/o, vref bank 4, l124p 4 y14 xc2s600e all i/o, vref bank 4, l124p i/o, vref bank 4, l124p_y i/o, l123n 4 af15 xc2s600e - i/o, l123n i/o, l123n_y i/o, l123p 4 ae15 xc2s600e - i/o, l123p i/o, l123p_y i/o 4 ab15 - - - i/o i/o, l122n_yy 4 aa15 all - i/o, l122n_yy i/o, l122n_yy i/o, l122p_yy 4 y15 all - i/o, l122p_yy i/o, l122p_yy i/o 4 af16 - - - i/o i/o, l121n_yy 4 w15 all - i/o, l121n_yy i/o, l121n_yy i/o, vref bank 4, l121p_yy 4 v15 all all i/o, vref bank 4, l121p_yy i/o, vref bank 4, l121p_yy i/o, l120n_yy 4 ae16 all - i/o, l120n_yy i/o, l120n_yy i/o, l120p_yy 4 ad16 all - i/o, l120p_yy i/o, l120p_yy i/o 4 ab16 - - - i/o i/o, l119n 4 aa16 - - i/o, l119n i/o, l119n i/o, l119p 4 y16 - - i/o, l119p i/o, l119p i/o 4 w16 - - - i/o i/o, l118n_yy 4 af17 all - i/o, l118n_yy i/o, l118n_yy i/o, l118p_yy 4 ae17 all - i/o, l118p_yy i/o, l118p_yy i/o, l117n_yy 4 ad17 all - i/o, l117n_yy i/o, l117n_yy i/o, l117p_yy 4 ac17 all - i/o, l117p_yy i/o, l117p_yy i/o 4 ab17 - - - i/o i/o, l116n 4 y17 xc2s600e - i/o, l116n i/o, l116n_y i/o, l116p 4 w17 xc2s600e - i/o, l116p i/o, l116p_y i/o 4 af18 - - - i/o i/o, l115n_yy 4 ae18 all - i/o, l115n_yy i/o, l115n_yy i/o, l115p_yy 4 ad18 all - i/o, l115p_yy i/o, l115p_yy fg676 pinouts (xc2s4 00e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 42 1-800-255-7778 product specification r i/o 4 ac18 - - i/o i/o i/o, vref bank 4, l114n 4 ab18 - all i/o, vref bank 4, l114n i/o, vref bank 4, l114n i/o, l114p 4 aa18 - - i/o, l114p i/o, l114p i/o, l113n 4 y18 - - i/o, l113n i/o, l113n i/o, l113p 4 w18 - - i/o, l113p i/o, l113p i/o 4 ab19 - - i/o i/o i/o, l112n 4 af19 xc2s600e - i/o i/o, l112n_y i/o, l112p 4 ae19 xc2s600e xc2s600e - i/o, vref bank 4, l112p_y i/o, l111n 4 aa19 xc2s600e - i/o, l111n i/o, l111n_y i/o, l111p 4 y19 xc2s600e - i/o, l111p i/o, l111p_y i/o 4 af20 - - - i/o i/o, l110n 4 ae20 xc2s600e - i/o, l110n i/o, l110n_y i/o, l110p 4 ad20 xc2s600e - i/o, l110p i/o, l110p_y i/o 4 ac20 - - i/o i/o i/o, l109n_yy 4 ab20 all - i/o, l109n_yy i/o, l109n_yy i/o, vref bank 4, l109p_yy 4 aa20 all all i/o, vref bank 4, l109p_yy i/o, vref bank 4, l109p_yy i/o 4 y20 - - i/o i/o i/o, l108n 4 af21 - - i/o, l108n i/o, l108n i/o, l108p 4 ae21 - - i/o, l108p i/o, l108p i/o, l107n 4 ad21 - - i/o, l107n i/o, l107n i/o, l107p 4 ac21 - - i/o, l107p i/o, l107p i/o 4 ac22 - - - i/o i/o, l106n_yy 4 af22 all - i/o, l106n_yy i/o, l106n_yy i/o, vref bank 4, l106p_yy 4 ae22 all all i/o, vref bank 4, l106p_yy i/o, vref bank 4, l106p_yy i/o, l105n_yy 4 ab21 all - i/o, l105n_yy i/o, l105n_yy i/o, l105p_yy 4 aa21 all - i/o, l105p_yy i/o, l105p_yy i/o, l104n_yy 4 af23 all - i/o, l104n_yy i/o, l104n_yy i/o, l104p_yy 4 ae23 all - i/o, l104p_yy i/o, l104p_yy i/o, l103n 4 ad23 xc2s600e - i/o i/o, l103n_y i/o, l103p 4 ae24 xc2s600e - - i/o, l103p_y i/o, l102n_yy 4 af24 all - i/o, l102n_yy i/o, l102n_yy i/o, l102p_yy 4 af25 all - i/o, l102p_yy i/o, l102p_yy fg676 pinouts (xc2s400e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 43 r done 3 ae26 - - done done program - ac24 - - program program i/o (init ), l101n_yy 3 ad25 all - i/o (init ), l101n_yy i/o (init ), l101n_yy i/o (d7), l101p_yy 3 ad26 all - i/o (d7), l101p_yy i/o (d7), l101p_yy i/o, l100n 3 ac25 - - - i/o, l100n i/o, l100p 3 ac26 - - - i/o, l100p i/o, l99n 3 ab22 xc2s600e - - i/o, l99n_y i/o, l99p 3 ab23 xc2s600e - i/o i/o, l99p_y i/o, l98n_yy 3 ab25 all - i/o, l98n_yy i/o, l98n_yy i/o, l98p_yy 3 ab26 all - i/o, l98p_yy i/o, l98p_yy i/o, l97n 3 aa23 - - i/o, l97n_y i/o, l97n i/o, l97p 3 aa24 - - i/o, l97p_y i/o, l97p i/o, vref bank 3, l96n 3 aa25 xc2s600e all i/o, vref bank 3, l96n i/o, vref bank 3, l96n_y i/o, l96p 3 aa26 xc2s600e - i/o, l96p i/o, l96p_y i/o, l95n 3 aa22 xc2s600e - - i/o, l95n_y i/o, l95p 3 y22 xc2s600e - i/o i/o, l95p_y i/o, l94n 3 y23 xc2s400e - i/o, l94n_y i/o, l94n i/o, l94p 3 y24 xc2s400e - i/o, l94p_y i/o, l94p i/o, l93n 3 y25 xc2s600e - i/o, l93n i/o, l93n_y i/o, l93p 3 y26 xc2s600e - i/o, l93p i/o, l93p_y i/o, vref bank 3, l92n_yy 3 w21 all all i/o, vref bank 3, l92n_yy i/o, vref bank 3, l92n_yy i/o, l92p_yy 3 w22 all - i/o, l92p_yy i/o, l92p_yy i/o 3 y21 - - - i/o i/o, l91n_yy 3 w25 all - i/o, l91n_yy i/o, l91n_yy i/o, l91p_yy 3 w26 all - i/o, l91p_yy i/o, l91p_yy i/o 3 w20 - - i/o i/o i/o, l90n 3 v19 xc2s400e - i/o, l90n_y i/o, l90n i/o, l90p 3 v20 xc2s400e - i/o, l90p_y i/o, l90p i/o, l89n 3 v21 xc2s600e xc2s600e - i/o, vref bank 3, l89n_y i/o, l89p 3 v22 xc2s600e - i/o i/o, l89p_y i/o 3 v23 - - i/o i/o i/o, l88n_yy 3 v24 all - i/o, l88n_yy i/o, l88n_yy fg676 pinouts (xc2s4 00e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 44 1-800-255-7778 product specification r i/o, l88p_yy 3 v25 all - i/o, l88p_yy i/o, l88p_yy i/o 3 v26 - - i/o i/o i/o, vref bank 3, l87n_yy 3 u19 all all i/o, vref bank 3, l87n_yy i/o, vref bank 3, l87n_yy i/o (d6), l87p_yy 3 u20 all - i/o (d6), l87p_yy i/o (d6), l87p_yy i/o (d5), l86n_yy 3 u22 all - i/o (d5), l86n_yy i/o (d5), l86n_yy i/o, l86p_yy 3 u23 all - i/o, l86p_yy i/o, l86p_yy i/o 3 u24 - - - i/o i/o, l85n 3 u25 xc2s600e - - i/o, l85n_y i/o, l85p 3 u26 xc2s600e - i/o i/o, l85p_y i/o 3 r18 - - i/o i/o i/o, l84n 3 t19 xc2s400e - i/o, l84n_y i/o, l84n i/o, l84p 3 t20 xc2s400e - i/o, l84p_y i/o, l84p i/o, l83n 3 t21 xc2s600e - i/o, l83n i/o, l83n_y i/o, l83p 3 t22 xc2s600e - i/o, l83p i/o, l83p_y i/o 3 t24 - - - i/o i/o, l82n 3 t25 xc2s600e - i/o, l82n i/o, l82n_y i/o, l82p 3 t26 xc2s600e - i/o, l82p i/o, l82p_y i/o 3 r19 - - - i/o i/o, l81n 3 r20 xc2s600e - i/o, l81n i/o, l81n_y i/o, l81p 3 r21 xc2s600e - i/o, l81p i/o, l81p_y i/o, vref bank 3, l80n_yy 3 r22 all all i/o, vref bank 3, l80n_yy i/o, vref bank 3, l80n_yy i/o (d4), l80p_yy 3 r23 all - i/o (d4), l80p_yy i/o (d4), l80p_yy i/o 3 p18 - - - i/o i/o, l79n_yy 3 r25 all - i/o, l79n_yy i/o, l79n_yy i/o, l79p_yy 3 r26 all - i/o, l79p_yy i/o, l79p_yy i/o 3 p19 - - - i/o i/o, l78n 3 p20 xc2s400e - i/o, l78n_y i/o, l78n i/o, l78p 3 p21 xc2s400e - i/o, l78p_y i/o, l78p i/o, vref bank 3, l77n 3 p22 xc2s600e all i/o, vref bank 3, l77n i/o, vref bank 3, l77n_y i/o, l77p 3 p23 xc2s600e - i/o, l77p i/o, l77p_y i/o 3 p24 - - - i/o i/o, l76n_yy 3 p25 all - i/o, l76n_yy i/o, l76n_yy i/o, l76p_yy 3 p26 all - i/o, l76p_yy i/o, l76p_yy fg676 pinouts (xc2s400e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 45 r i/o 3 n18 - - - i/o i/o (trdy) 3 n24 - - i/o (trdy) i/o (trdy) i/o (irdy), l75n_yy 2 n26 all - i/o (irdy), l75n_yy i/o (irdy), l75n_yy i/o, l75p_yy 2 n25 all - i/o, l75p_yy i/o, l75p_yy i/o 2 n19 - - - i/o i/o, l74n 2 n23 xc2s600e - - i/o, l74n_y i/o, l74p 2 n22 xc2s600e - i/o i/o, l74p_y i/o 2 m23 - - i/o i/o i/o, l73n 2 n21 xc2s600e - i/o, l73n i/o, l73n_y i/o, vref bank 2, l73p 2 n20 xc2s600e all i/o, vref bank 2, l73p i/o, vref bank 2, l73p_y i/o, l72n 2 m26 xc2s400e - i/o, l72n_y i/o, l72n i/o, l72p 2 m25 xc2s400e - i/o, l72p_y i/o, l72p i/o 2 m22 - - - i/o i/o, l71n_yy 2 m21 all - i/o, l71n_yy i/o, l71n_yy i/o, l71p_yy 2 m20 all - i/o, l71p_yy i/o, l71p_yy i/o 2 l26 - - - i/o i/o (d3), l70n_yy 2 m19 all - i/o (d3), l70n_yy i/o (d3), l70n_yy i/o, vref bank 2, l70p_yy 2 m18 all all i/o, vref bank 2, l70p_yy i/o, vref bank 2, l70p_yy i/o, l69n 2 l25 xc2s600e - i/o, l69n i/o, l69n_y i/o, l69p 2 l24 xc2s600e - i/o, l69p i/o, l69p_y i/o 2 l22 - - - i/o i/o, l68n 2 l21 xc2s600e - i/o, l68n i/o, l68n_y i/o, l68p 2 l20 xc2s600e - i/o, l68p i/o, l68p_y i/o 2 l19 - - - i/o i/o, l67n 2 k26 xc2s600e - i/o, l67n i/o, l67n_y i/o, l67p 2 k25 xc2s600e - i/o, l67p i/o, l67p_y i/o, l66n 2 k24 - - - i/o, l66n i/o, l66p 2 k23 - - i/o i/o, l66p i/o 2 k22 - - - i/o i/o, l65n 2 k20 xc2s600e - i/o i/o, l65n_y i/o, l65p 2 k19 xc2s600e - i/o i/o, l65p_y i/o 2 j26 - - i/o i/o fg676 pinouts (xc2s4 00e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 46 1-800-255-7778 product specification r i/o, l64n_yy 2 j25 all - i/o, l64n_yy i/o, l64n_yy i/o (d2), l64p_yy 2 j24 all - i/o (d2), l64p_yy i/o (d2), l64p_yy i/o (d1) 2 j23 - - i/o (d1) i/o (d1) i/o, vref bank 2, l63n_yy 2 j22 all all i/o, vref bank 2, l63n_yy i/o, vref bank 2, l63n_yy i/o, l63p_yy 2 j21 all - i/o, l63p_yy i/o, l63p_yy i/o, l62n_yy 2 j20 all - i/o, l62n_yy i/o, l62n_yy i/o, l62p_yy 2 j19 all - i/o, l62p_yy i/o, l62p_yy i/o 2 h22 - - i/o i/o i/o, l61n 2 h26 xc2s600e - i/o i/o, l61n_y i/o, l61p 2 h25 xc2s600e xc2s600e - i/o, vref bank 2, l61p_y i/o, l60n 2 h21 xc2s400e - i/o, l60n_y i/o, l60n i/o, l60p 2 h20 xc2s400e - i/o, l60p_y i/o, l60p i/o 2 g26 - - - i/o i/o, l59n_yy 2 g25 all - i/o, l59n_yy i/o, l59n_yy i/o, l59p_yy 2 g24 all - i/o, l59p_yy i/o, l59p_yy i/o 2 g23 - - i/o i/o i/o, l58n_yy 2 g22 all - i/o, l58n_yy i/o, l58n_yy i/o, vref bank 2, l58p_yy 2 g21 all all i/o, vref bank 2, l58p_yy i/o, vref bank 2, l58p_yy i/o 2 g20 - - i/o i/o i/o, l57n_yy 2 f26 all - i/o, l57n_yy i/o, l57n_yy i/o, l57p_yy 2 f25 all - i/o, l57p_yy i/o, l57p_yy i/o, l56n 2 f24 xc2s600e - i/o, l56n i/o, l56n_y i/o, l56p 2 f23 xc2s600e - i/o, l56p i/o, l56p_y i/o 2 f22 - - - i/o i/o, l55n 2 e26 xc2s600e - i/o, l55n i/o, l55n_y i/o, vref bank 2, l55p 2 e25 xc2s600e all i/o, vref bank 2, l55p i/o, vref bank 2, l55p_y i/o, l54n 2 e23 xc2s400e - i/o, l54n_y i/o, l54n i/o, l54p 2 e22 xc2s400e - i/o, l54p_y i/o, l54p i/o, l53n_yy 2 f21 all - i/o, l53n_yy i/o, l53n_yy i/o, l53p_yy 2 e21 all - i/o, l53p_yy i/o, l53p_yy i/o, l52n 2 d26 xc2s600e - i/o i/o, l52n_y i/o, l52p 2 d25 xc2s600e - - i/o, l52p_y fg676 pinouts (xc2s400e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 47 r i/o, l51n 2 d24 - - - i/o, l51n i/o, l51p 2 c25 - - - i/o, l51p i/o (din, d0), l50n_yy 2 c26 all - i/o (din, d0), l50n_yy i/o (din, d0), l50n_yy i/o (dout, busy), l50p_yy 2 b26 all - i/o (dout, busy), l50p_yy i/o (dout, busy), l50p_yy cclk 2 a25 - - cclk cclk tdo 2 c23 - - tdo tdo tdi - d22 - - tdi tdi i/o (cs ), l49p_yy 1 b24 all - i/o (cs ), l49p_yy i/o (cs ), l49p_yy i/o (write ), l49n_yy 1 a24 all - i/o (write ), l49n_yy i/o (write ), l49n_yy i/o, l48p 1 b23 - - i/o i/o, l48p i/o, l48n 1 a23 - - - i/o, l48n i/o, l47p 1 b22 xc2s400e - i/o, l47p_y i/o, l47p i/o, l47n 1 a22 xc2s400e - i/o, l47n_y i/o, l47n i/o, l46p_yy 1 d21 all - i/o, l46p_yy i/o, l46p_yy i/o, l46n_yy 1 c21 all - i/o, l46n_yy i/o, l46n_yy i/o, vref bank 1, l45p_yy 1 b21 all all i/o, vref bank 1, l45p_yy i/o, vref bank 1, l45p_yy i/o, l45n_yy 1 a21 all - i/o, l45n_yy i/o, l45n_yy i/o, l44p 1 f20 xc2s600e - - i/o, l44p_y i/o, l44n 1 e20 xc2s600e - i/o i/o, l44n_y i/o, l43p_yy 1 d20 all - i/o, l43p_yy i/o, l43p_yy i/o, l43n_yy 1 c20 all - i/o, l43n_yy i/o, l43n_yy i/o, l42p_yy 1 b20 all - i/o, l42p_yy i/o, l42p_yy i/o, l42n_yy 1 a20 all - i/o, l42n_yy i/o, l42n_yy i/o, vref bank 1, l41p_yy 1 g19 all all i/o, vref bank 1, l41p_yy i/o, vref bank 1, l41p_yy i/o, l41n_yy 1 f19 all - i/o, l41n_yy i/o, l41n_yy i/o 1 e19 - - - i/o i/o, l40p_yy 1 b19 all - i/o, l40p_yy i/o, l40p_yy i/o, l40n_yy 1 a19 all - i/o, l40n_yy i/o, l40n_yy i/o 1 h18 - - i/o i/o i/o, l39p 1 g18 xc2s600e - i/o, l39p i/o, l39p_y fg676 pinouts (xc2s4 00e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 48 1-800-255-7778 product specification r i/o, l39n 1 f18 xc2s600e - i/o, l39n i/o, l39n_y i/o, l38p 1 d18 xc2s600e xc2s600e - i/o, vref bank 1, l38p_y i/o, l38n 1 c18 xc2s600e - i/o i/o, l38n_y i/o, l37p_yy 1 b18 all - i/o, l37p_yy i/o, l37p_yy i/o, l37n_yy 1 a18 all - i/o, l37n_yy i/o, l37n_yy i/o, l36p_yy 1 h17 all - i/o, l36p_yy i/o, l36p_yy i/o, l36n_yy 1 g17 all - i/o, l36n_yy i/o, l36n_yy i/o, vref bank 1, l35p_yy 1 e18 all all i/o, vref bank 1, l35p_yy i/o, vref bank 1, l35p_yy i/o, l35n_yy 1 e17 all - i/o, l35n_yy i/o, l35n_yy i/o, l34p_yy 1 d17 all - i/o, l34p_yy i/o, l34p_yy i/o, l34n_yy 1 c17 all - i/o, l34n_yy i/o, l34n_yy i/o 1 h16 - - - i/o i/o, l33p 1 b17 xc2s600e - i/o, l33p i/o, l33p_y i/o, l33n 1 a17 xc2s600e - i/o, l33n i/o, l33n_y i/o 1 g16 - - - i/o i/o, l32p_yy 1 f16 all - i/o, l32p_yy i/o, l32p_yy i/o, l32n_yy 1 e16 all - i/o, l32n_yy i/o, l32n_yy i/o, l31p_yy 1 c16 all - i/o, l31p_yy i/o, l31p_yy i/o, l31n_yy 1 b16 all - i/o, l31n_yy i/o, l31n_yy i/o 1 a16 - - - i/o i/o, l30p 1 j15 - - i/o, l30p i/o, l30p i/o, l30n 1 h15 - - i/o, l30n i/o, l30n i/o 1 g15 - - - i/o i/o, l29p_yy 1 f15 all - i/o, l29p_yy i/o, l29p_yy i/o, l29n_yy 1 e15 all - i/o, l29n_yy i/o, l29n_yy i/o, vref bank 1, l28p_yy 1 b15 all all i/o, vref bank 1, l28p_yy i/o, vref bank 1, l28p_yy i/o, l28n_yy 1 a15 all - i/o, l28n_yy i/o, l28n_yy i/o 1 d15 - - - i/o i/o, l27p_yy 1 j14 all - i/o, l27p_yy i/o, l27p_yy i/o, l27n_yy 1 h14 all - i/o, l27n_yy i/o, l27n_yy i/o 1 g14 - - - i/o i/o, l26p 1 f14 xc2s600e - i/o, l26p i/o, l26p_y i/o, l26n 1 e14 xc2s600e - i/o, l26n i/o, l26n_y fg676 pinouts (xc2s400e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 49 r i/o, vref bank 1, l25p 1 d14 xc2s600e all i/o, vref bank 1, l25p i/o, vref bank 1, l25p_y i/o, l25n 1 c14 xc2s600e - i/o, l25n i/o, l25n_y i/o 1 j13 - - - i/o i/o, l24p 1 c13 - - i/o, l24p i/o, l24p i/o, l24n 1 d13 - - i/o, l24n i/o, l24n i/o 1 h13 - - - i/o i/o (dll), l23p 1 b14 - - i/o (dll), l23p i/o (dll), l23p gck2, i 1 a14 - - gck2, i gck2, i gck3, i 0 a13 - - gck3, i gck3, i i/o (dll), l23n 0 b13 - - i/o (dll), l23n i/o (dll), l23n i/o 0 e13 - - - i/o i/o, l22p_yy 0 f13 all - i/o, l22p_yy i/o, l22p_yy i/o, l22n_yy 0 g13 all - i/o, l22n_yy i/o, l22n_yy i/o, l21p 0 a12 xc2s600e - - i/o, l21p_y i/o, vref bank 0, l21n 0 b12 xc2s600e all i/o, vref bank 0 i/o, vref bank 0, l21n_y i/o, l20p 0 d12 xc2s600e - i/o, l20p i/o, l20p_y i/o, l20n 0 e12 xc2s600e - i/o, l20n i/o, l20n_y i/o 0 f12 - - - i/o i/o, l19p_yy 0 g12 all - i/o, l19p_yy i/o, l19p_yy i/o, l19n_yy 0 h12 all - i/o, l19n_yy i/o, l19n_yy i/o 0 j12 - - - i/o i/o, l18p_yy 0 a11 all - i/o, l18p_yy i/o, l18p_yy i/o, vref bank 0, l18n_yy 0 b11 all all i/o, vref bank 0, l18n_yy i/o, vref bank 0, l18n_yy i/o, l17p_yy 0 e11 all - i/o, l17p_yy i/o, l17p_yy i/o, l17n_yy 0 f11 all - i/o, l17n_yy i/o, l17n_yy i/o 0 c11 - - - i/o i/o, l16p 0 g11 - - i/o, l16p i/o, l16p i/o, l16n 0 h11 - - i/o, l16n i/o, l16n i/o 0 c10 - - - i/o i/o, l15p_yy 0 a10 all - i/o, l15p_yy i/o, l15p_yy i/o, l15n_yy 0 b10 all - i/o, l15n_yy i/o, l15n_yy i/o, l14p_yy 0 d10 all - i/o, l14p_yy i/o, l14p_yy fg676 pinouts (xc2s4 00e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 50 1-800-255-7778 product specification r i/o, l14n_yy 0 e10 all - i/o, l14n_yy i/o, l14n_yy i/o 0 g10 - - - i/o i/o, l13p 0 a9 xc2s600e - i/o, l13p i/o, l13p_y i/o, l13n 0 b9 xc2s600e - i/o, l13n i/o, l13n_y i/o 0 h10 - - - i/o i/o, l12p_yy 0 c9 all - i/o, l12p_yy i/o, l12p_yy i/o, l12n_yy 0 d9 all - i/o, l12n_yy i/o, l12n_yy i/o 0 e9 - - i/o i/o i/o, vref bank 0, l11p 0 f9 - all i/o, vref bank 0, l11p i/o, vref bank 0, l11p i/o, l11n 0 g9 - - i/o, l11n i/o, l11n i/o, l10p 0 a8 - - i/o, l10p i/o, l10p i/o, l10n 0 b8 - - i/o, l10n i/o, l10n i/o 0 h9 - - i/o i/o i/o, l9p 0 e8 xc2s600e - i/o i/o, l9p_y i/o, l9n 0 f8 xc2s600e xc2s600e - i/o, vref bank 0, l9n_y i/o, l8p 0 a7 xc2s600e - i/o, l8p i/o, l8p_y i/o, l8n 0 b7 xc2s600e - i/o, l8n i/o, l8n_y i/o 0 g8 - - i/o i/o i/o, l7p_yy 0 c7 all - i/o, l7p_yy i/o, l7p_yy i/o, l7n_yy 0 d7 all - i/o, l7n_yy i/o, l7n_yy i/o 0 e7 - - - i/o i/o, l6p_yy 0 f7 all - i/o, l6p_yy i/o, l6p_yy i/o, vref bank 0, l6n_yy 0 g7 all all i/o, vref bank 0, l6n_yy i/o, vref bank 0, l6n_yy i/o 0 a6 - - i/o i/o i/o, l5p 0 b6 - - i/o, l5p i/o, l5p i/o, l5n 0 c6 - - i/o, l5n i/o, l5n i/o, l4p 0 d6 - - i/o, l4p i/o, l4p i/o, l4n 0 e6 - - i/o, l4n i/o, l4n i/o 0 f6 - - - i/o i/o, l3p_yy 0 a5 all - i/o, l3p_yy i/o, l3p_yy i/o, vref bank 0, l3n_yy 0 b5 all all i/o, vref bank 0, l3n_yy i/o, vref bank 0, l3n_yy i/o, l2p_yy 0 d5 all - i/o, l2p_yy i/o, l2p_yy fg676 pinouts (xc2s400e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 51 r i/o, l2n_yy 0 e5 all - i/o, l2n_yy i/o, l2n_yy i/o, l1p_yy 0 b4 all - i/o, l1p_yy i/o, l1p_yy i/o, l1n_yy 0 c4 all - i/o, l1n_yy i/o, l1n_yy i/o, l0p 0 a3 xc2s600e - i/o i/o, l0p_y i/o, l0n 0 b3 xc2s600e - - i/o, l0n_y i/o 0 a4 - - i/o i/o tck - a2 - - tck tck fg676 differential clock pins clock bank p input n input pin name pin name gck0 4 af14 gck0, i ae14 i/o (dll), l126p gck1 5 af13 gck1, i ae13 i/o (dll), l126n gck2 1 a14 gck2, i b14 i/o (dll), l23p gck3 0 a13 gck3, i b13 i/o (dll), l23n fg676 pinouts (xc2s4 00e, xc2s600e) (continued) pad name pin lvds async. output option vref option device-specific pinouts function bank xc2s400e xc2s600e additional fg676 package pins vccint pins h8 h19 j9 j18 k10 k11 k16 k17 l10 l17 t10 t17 u10 u11 u16 u17 v9 v18 w8 w19 - vcco bank 0 pins c5 c8 d11 j10 j11 k12 k13 vcco bank 1 pins c19 c22 d16 j16 j17 k14 k15 vcco bank 2 pins e24 h24 k18 l18 l23 m17 n17 vcco bank 3 pins p17 r17 t18 t23 u18 w24 ab24 vcco bank 4 pins u14 u15 v16 v17 ac16 ad19 ad22 vcco bank 5 pins u12 u13 v10 v11 ac11 ad5 ad8 vcco bank 6 pins p10 r10 t4 t9 u9 w3 ab3 vcco bank 7 pins h3 k9 l4 l9 m10 n10 e3
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 52 1-800-255-7778 product specification r gnd pins a1 a26 b2 b25 c3 c12 c15 c24 d4 d8 d19 d23 f10 f17 h4 h23 k6 k21 l11 l12 l13 l14 l15 l16 m3 m11 m12 m13 m14 m15 m16 m24 n11 n12 n13 n14 n15 n16 p11 p12 p13 p14 p15 p16 r3 r11 r12 r13 r14 r15 r16 r24 t11 t12 t13 t14 t15 t16 u6 u21 w4 w23 aa10 aa17 ac4 ac8 ac19 ac23 ad3 ad12 ad15 ad24 ae2 ae25 af1 af26 - not connected pins (xc2s400e only) a12 a16 a23 b3 c1 c2 c10 c11 c25 d2 d15 d18 d24 d25 e7 e13 e19 f2 f6 f8 f12 f20 f22 g10 g14 g15 g16 g26 h10 h13 h16 h25 j6 j8 j12 j13 k1 k4 k22 k24 l3 l19 l22 l26 m4 m9 m22 n1 n4 n9 n18 n19 n23 p4 p5 p18 p19 p24 r4 r7 r19 t3 t24 u1 u4 u7 u24 u25 v8 v12 v13 v21 w12 w13 w14 w16 y3 y7 y21 aa7 aa9 aa22 ab15 ab16 ab17 ab22 ac1 ac15 ac22 ac25 ac26 ad1 ad2 ad10 ad11 ad13 ad14 ae5 ae19 ae24 af4 af16 af18 af20 - additional fg676 package pins (continued)
spartan-iie 1.8v fpga family: pinout tables ds077-4 (2.1) february 14, 2003 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 53 r revision history the spartan-iie family data sheet ds077-1 , spartan-iie 1.8v fpga family: introduction and ordering information (module 1) ds077-2 , spartan-iie 1.8v fpga family: functional description (module 2) ds077-3 , spartan-iie 1.8v fpga family: dc and switching characteristics (module 3) ds077-4 , spartan-iie 1.8v fpga family: pinout tables (module 4) version no. date description 1.0 11/15/01 initial xilinx release. 1.1 12/20/01 corrected differential pin pair designations. 2.0 11/18/02 added xc2s400e and xc2s600e and fg676. removed l37 designation from ft256 pinouts. minor corrections and clarifications to pinout definitions. removed preliminary designation. 2.1 02/14/03 added differential pairs table on page 3 , fixed 3 p/n designation typos introduced in v2.0. clarified that xc2s50e has two vref pins per bank.
spartan-iie 1.8v fpga family: pinout tables module 4 of 4 www.xilinx.com ds077-4 (2.1) february 14, 2003 54 1-800-255-7778 product specification r

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